1.1 Introduction
1.2 What Is Verification?
1.3 Verification as It Was
1.4 A New Beginning
1.5 Formal Methods
1.6 Coverage
1.7 Systems on Chip
1.8 Diverse Options

2.1 The Verification Landscape
2.2 A Brief Introduction to SystemVerilog
2.3 The Property Specification Language
2.4 A Brief Introduction to SystemC
2.5 A Brief Introduction to e
2.6 Verification Languages - Conclusion

3.1 Introduction
3.2 The Driver of Standards
3.3 Design and Verification Challenges
3.4 The Value of Standards

4.1 Introduction
4.2 Standalone VC Functional Verification
4.3 Emerging VC Verification Approaches
4.4 VC Integration Verification
4.5 VSIA Functional Verification Efforts
4.6 Conclusion

5.1 TEN: Do It Up Front - Do It Now!
5.2 NINE: Buy-In - Do It Together
5.3 EIGHT: KISS
5.4 SEVEN: Mission Statement
5.5 SIX: Yellow Sticky Method
5.6 FIVE: Architect a Verification System
5.7 FOUR: Generation
5.8 THREE: Checking
5.9 TWO: Coverage
5.10 ONE: Automation
5.11 Conclusion

6.1 Introduction
6.2 Taxonomy of Modeling Styles
6.3 Comparing Predications against Implementations
6.4 When Predication Becomes Impossible
6.5 Why Care about "Don't Cares"?
6.6 Separating Models from Simulators
6.7 Implementing Transaction Synchronization
6.8 Validating A Synchronized Model
6.9 Looking toward the Future
6.10 Summary

7.1 Introduction
7.2 Artifacts of Simulation
7.3 Line of Intent
7.4 Integrating Formal into the Verification Flow
7.5 Overcoming Formal Tool Capacity Limitations
7.6 Conclusion

8.1 Introduction
8.2 Common Coding Problems
8.3 Cost Comparisons
8.4 Lint Usage Methodologies
8.5 Future Directions
8.6 Conclusion

9.1 Introduction
9.2 Hardware/Software Interaction
9.3 Multiple Levels of Abstraction
9.4 The Basics of Practical Co-Verification
9.5 Performance Fundamentals
9.6 The Hardware/Software Relationship
9.7 Conceptual Design Flow
9.8 Implementing Co-Simulation Solutions
9.9 Conclusion

10.1 Introduction
10.2 Background and the Evolution of Coverage
10.3 Developing Functional and Assertion Coverage Items
10.4 Auto-Generating Functional and Assertion Coverage Items
10.5 Using Functional and Assertion Coverage Statistics
10.6 Conclusion

11.1 Introduction
11.2 Digital Functional Verification Strategy
11.3 Analog Discrete Time Modeling
11.4 A Unified Analog-Digital Approach
11.5 Conclusion

12.1 Introduction
12.2 Random vs. Directed Stimulus
12.3 Randomization in SystemVerilog
12.4 Randomization and Object-Oriented Programming
12.5 Interacting with the DUT: Transactors
12.6 Higher-Level Transactions
12.7 Communication between Testbench Layers
12.8 Results Checking
12.9 Generating Exceptions
12.10 Conclusion

13.1 Introduction
13.2 The Evolution of Debug and Its Automation
13.3 Automating Trace-Based Debug
13.4 Raising the Abstraction Level of Implementation Debug
13.5 Higher-Level Debug Approaches
13.6 Putting It All Together: Debug from System to Implementation

14.1 Introduction
14.2 The Verification Approach
14.3 Key Challenges
14.4 Key Learnings
14.5 Smarter Debugging Tips
14.6 Conclusion and Future Directions

15.1 Introduction
15.2 A Modular Mixed-Signal Testbench Structure
15.3 Virtual Test Equipment Devices
15.4 A Mixed-Signal Verification Example with Virtual Test Equipment
15.5 A Proposed Unified Verification and Validation Platform
15.6 Conclusion

16.1 Introduction
16.2 Assertions
16.3 Simulation-Based Verification with Assertions
16.4 Formal Verification with Assertions
16.5 Verification Hot Spots
16.6 Verification Hot Spot #1: Arbiters
16.7 Verification Hot Spot #2: Bus Interfaces and Bridges
16.8 Verification Hot Spot #3: Memory, DMA, and External Device Controllers
16.9 Verification Hot Spot #4: Resource Sharing
16.10 Verification Hot Spot #5: Clock Domains
16.11 Verification Results
16.12 Conclusion

17.1 Introduction
17.2 An Overview of TC2 Verification
17.3 The Key Block
17.4 Reachable State Considerations
17.5 Checking Properties in Simulation
17.6 How Properties Are Developed
17.7 Automated Checks
17.8 Results
17.9 Conclusion

18.1 Introduction
18.2 Verification of a Configured Processor
18.3 Verification of Customer Extensions
18.4 Verification of Multiple Configurations
18.5 Deliverables for SoC Design, Integration, and Verification
18.6 Future Trends in Verification and Their Impact