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Figure 12.
Figure 13.
Additional materials and line widths will be considered in the passive system.
The optimized passive system test fixture consisted of two low-loss daughtercards (σ~0.004) with uncoupled 8 mil transmission lines, nonstandard plated through hole signal launches, and a three-inch path length. The backplane used was constructed out of a low-loss material (σ~0.004) with coupled 8 and 12 mil transmission lines, nonstandard board launches, five- and 10-inch trace lengths.
Figure 14.
Figure 15.
An eye opening of 17 percent of its original value (85 mV) can be achieved at path lengths up to 16 inches. The measured system utilized all of the optimized parameters discussed in this paper (large trace widths, small diameter plated through holes, nonstandard anti-pads, and a high-speed differential connector). In an integrated system design, all components must be optimized to achieve system performance (bandwidth) at data rates in excess of 10 Gbps. With rates increasing in 4X increments, traditional design rules must be rewritten and incorporated with other anomalies that will occur in a system designed for these speeds.
Figure 16.
In this section, we will be looking at the characteristics of the passive backplane system with standard clearances, no attempt to reduce stub length, or any of the other modifications done in the previous optimize passive backplane section. The passive backplane system consists of a backplane made from different material and trace lengths with two mated backplane connectors. Essentially, the signal will be passed from one daughtercard through the connector, then the backplane, and then through another connector and out through a SMA connection.
A picture of one of the passive backplane systems with SMA connector daughtercards is shown in Figure 17.
Figure 17.
The various backplane material, trace length, and connectors that will be evaluated are shown in Figure 17. For the entire passive system test, a 2e23 pseudo-random pattern length was used with a 500 mV swing. The backplanes were approximately 0.2" thick and had 8 mil lines and spaces for a 100-ohm differential impedance. The daughtercards were routed single ended, with a 50-ohm impedance, and were approximately 0.1" thick. The VHDM-HSD daughtercard incorporates the non-circular clearance similar to that used on the backplane. This is shown in Figure 18. The GbX daughtercard does not use the non-circular clearance; instead, a standard circular clearance was used. This will result in data that will not be as good as if the non-circular clearance had been used. In Figure 18, the routing for GbX is very similar to VHDM-HSD.
Figure 18.
The first analysis was done with a 20" trace length in FR, Megtron, and Rogers with the VHDM-HSD eight-row connector at a data rate of 5 Gbps. The eye patterns in Figure 18 are organized in the following fashion: FR4 top left, Megtron top right, and Rogers bottom middle. The Rogers 4350 is clearly the best performer of these three materials. It provides 49 ps of less jitter (113 ps versus 64 ps) and nearly 100 mV of additional eye opening (60 mV versus 160 mV) than FR4.
The next analysis was done with a 10" trace length in FR4, Megtron, and Rogers with the VHDM-HSD eight-row connector at a data rate of 5 Gbps. The eye patterns in Figure 18 are organized in the following fashion: FR4 top left, Megtron top right, and Rogers bottom middle. The Rogers 4350 is clearly the best performer of these three materials. It provides 49 ps of less jitter (69 ps versus 41 ps) while all the materials had >100 mV of eye opening. This shows that the system performance at 10" has less sensitivity to laminates as it does at 20".
GbX was analyzed at 10" of Rogers plus 6" of total DC length in FR4 at 4, 5, and 6 Gbps. It is obvious that the system performance degrades rapidly from 4 Gbps to 6 Gbps. The 6 Gbps data rate is still passing by the standard of having at least 100 mV of eye opening.
A summary of the data rates that are achievable through various laminates and trace lengths are shown in Figure 18. The criterion was that the eye opening had to be at least 100 mV or 20 percent of the 500 mV output voltage swing.
In this section, the passive backplane system will be replaced by an active system. The active system consists primarily of an OC–192 serdes chip set and a 622 Mhz parallel loop-back board supplied by AMCC.
The passive system was enhanced by incorporating AMCC's S3091, an OC–192 serializer and S3092, and an OC–192 deserializer that contains a CDR. The CDR, along with the serialzer/deserializer, will be evaluated for passing these high-speed signals.
First Just One Signal Path
The 10 Gbps testbed was designed to demonstrate a bidirectional serial transmission of 10 Gbps data streams across backplanes. An intermediate 622 MHz data bus pass-thru card was used to simulate data bus traffic on a line card.
A 10 Gbps BERT was used to drive the SMA inputs to the Card 1 Rx. This Rx is located on the upper OC–192 card, which is connected to the backplane OC–192 card by the 622 MHz data bus pass-thru card. The backplane OC–192 card is Card 2 in the signal path. The Tx of Card 2 then drives the backplane at 10 Gbps to the OC–192 Card 3 Rx.
The Card 3 Rx receives the 10 Gbps serial data and sends it up the 622 Mbps data bus of the pass-thru card. If a loop-back card is installed at the upper OC–192 card location, it sends the 622 Mbps data back to the Card 3 Tx. The Card 3 Tx then sends the 10 Gbps serial data back to the Card 2 Rx. The OC–192 Card 2 Rx then drives the 622 Mbps data bus of the pass-thru card up to the upper OC–192 Card 1 Tx. And again, the Card 1 Tx sends the 10 Gbps data back to the BERT and communications analyzer. The BERT gives data bit-error-rate information, and the communication analyzer allows viewing of the signal quality and eye diagram of the final signal.
Figure 19.
Signal Path Options
Note that there are two types of Card 2s and Card 3s; one set uses VHDM-HSD connectors, and another uses GbX connectors. There are identical paths in the testbed backplane for each connector type. There are also two data-path lengths through the backplane: 10" and 20".
Another option is to have another OC–192 type, like Card 1, to take the Card 3 622 MHz output and send it back to the BERT in serial 10 Gbps format after only one pass through the backplane. This would replace the data bus loop-back card. A third option is to use our original OC–192 loop-back card with the Card 3 backplane interface cards in place of the Card 3 pass-thru loop-back combination.
The active system uses AMCC's S3091 and te OC–192 serializer as the transit portion of the link. AMCC's S3092 deserializer was used as the receiver portion of the link. The S3091 serializer takes the 622 Mbps, 16-bit wide differential data bus and serializes the data into a 10 Gbps data stream. The output of the S3091 is a current mode logic (CML) driver. This output will drive into the backplane, demonstrating performance through Teradyne's VHDM-HSD™ and GbX™ backplane connectors.
The S3092 deserializer has a 6 dB boost amp ahead of its CDR circuits. The CDR will recover clock timing of the incoming data, removing jitter caused by the backplane and connector transitions.
With the recovered timing of the incoming data, the lockdet signal will indicate a completed connection with qualified data.
Figure 20.
Figure 20 shows the combination board set used for the AMCC OC–192 Chip Set Evaluation Platform. The smaller board shows the S3091 and S3092 BGAs. The larger board shown under the small board is the 622 MHz data bus loop-back board. The loop-back board also contains SMA connectors to bring in external synchronization clocks and power to both cards. A small power interlock circuit also maintains the correct power up sequencing no matter when the external supplies are powered up.
See your local AMCC representative or visit the AMCC Web site at www.AMCC.com for S3091/53092 chip specifics.
The specifics of 10 Gbps design are shown in Figure 21, which is a layout of one of the backplane interface cards. Co-planar waveguide structures are used to enter and exit the 10 Gbps ports of the BGAs. These structures are then lined with vias to assist in maintaining the edge speeds of the signals. These edge speeds are on the order of 25 to 35 ps rise and fall times.
Figure 21.
The top layer of this PCB is made up of RO-4003 material. This material is easy to work with in a hybrid stack-up of GETEK or HT-FR4.
Inner traces for the 622 Mbps data bus are shown in Figure 22. Matched length considerations are highlighted in the bullets.
Figure 22.
The key to matched length design is to come up with an allowable system skew budget, and then to distribute those budget pieces over the cards affected. Manufacturing tolerances or board layout considerations will all come into the picture. Connector and via effects must also be taken into account. Board materials for these layers may be different than for the top high-speed layer. One method that has been used with success is making a spreadsheet with all of the effects represented and totaled at the bottom. This allows most of the effects of a high-speed design to be consistently taken into account.
OC–192 board testing involves checking out each functional signal path. If these signal paths can be verified individually, you will build a system on a solid foundation and save yourself a lot of checkout time at the system level.
This can be accomplished by checking out each OC–192 card individually before they are integrated into the system testbed.
After testing the OC–192 cards individually, you are ready to integrate them into a 622 Mbps pass-thru card assembly. The first eye diagram in Figure 23 shows the output from the backplane test fixture and the OC–192 card with a VHDM-HSD connector. Note that the backplane test fixture PCB has 6" of traces in FR4 material.
The second eye diagram in Figure 23 shows the output of a similar backplane test fixture and the OC-192 card with a GbX connector.
Figure 23.
The first cut at the complete testbed running together is shown in Figure 24. Follow the slide bullets for the signal path. Note that each time the 10 Gbps signal transitions into an S3092 Rx, the CDR will clean up the jitter. Therefore, the final jitter out of the last OC–192 card into the BERT will mostly have the jitter associated with the final trace paths of the last OC–192 Tx and the cables to the BERT. Therefore, if you look at the eye diagram on the communications analyzer, you will see a very nice OC–192 eye with ~20 ps of jitter.
Figure 24.
The eye diagrams in Figure 25 show the difference between a BERT driving a 10" Rogers backplane with GbX connectors and the S3091 Tx driving the same backplane. The only difference is that the BERT is driving its cables and 3" more of FR4.
Figure 25.
The eye diagram in Figure 26 shows a 10 Gbps data rate being passed through two GbX connectors and 10" of a Rogers 4350 backplane. In addition, a set of AMCC S3091/S3092 10 Gbps Serdes chip sets was used on both GbX daughtercards. A detailed description of the S3091/92 chip set and the GbX connector can be found in previous slides. It is clear that with the aid of the AMCC SerDes and using a high-performance connector, such as GbX and high-performance materials (Rogers 4350), that 10Gbps data rates can be achieved in a backplane environment. The backplane did not incorporate any of the techniques previously described in reducing the capacitive effect of the plated through hole, such as counter boring, dual-density drilling, or minimization of the stub effect. The only feature used was the non-circular anti-pad around the signal pairs.
Figure 26.
Currently, we are integrating all of the pieces of the 10 Gbps serial backplane testbed. Initial results have shown eye diagrams that are reasonable to work with. Further testing will quantify what acceptable backplane lengths are for current 10 Gbps technology.
The OC–192 cards have been fabricated and are currently in testing. Some initial test results with the backplane test cards have shown an improved eye between the VHDM-HSD and the GbX connectors.
Signal-integrity testing will start soon with TDR and network-analyzer measurements. This will quantify the complete system performance and any improvement suggestions for PCB matching at 10 Gbps with the VHDM-HSD and GbX connectors.
