PDF of this tutorialThe elements considered in this study include trace topology, laminate material, high-speed backplane connectors, and the launch effects due to the plated through via. The elements will be individually characterized through measurements, then combined and measured as a passive system. The intent is not to provide a detailed study on any of the elements, but rather to reduce the variables in the system for a first cut at the most promising combined solution.
Finally, optical carrier (OC)–192 devices were added to the system to take measurements on a realistic fully active system and to determine the performance gains provided by the chip set through means such as clock and data recovery (CDR). The information gained will be useful in future efforts to optimize 10 Gbps systems but also to provide design guidelines at lower data rates.
The connectors used in this study are internally shielded, 100Ω matched impedance connectors designed for backplane systems. Measurements will be shown for the Teradyne VHDM-HSD and Teradyne GbX connectors. The intent is not to do a detailed connector comparison, but rather to characterize high-speed systems with two high-performance differential connectors. Because connector density can be a constraint in backplane system design, the representative interconnects selected also had to have a high density of real signals (signal pairs after ground assignments). The measured VHDM-HSD connector provides 38 real pairs per inch while GbX provides 55 real pairs per inch.
The electrical characterization of a high-speed connector is typically reported as interpair crosstalk and connector/launch impedance.
In typical backplane application, the connector is seen at least twice by the signal as it passes from card to card, and therefore must not excessively attenuate the signal. Any connector intended for high-speed design will need low multi-pin crosstalk in spite of a need for a high-density interface. GbX achieves these requirements by closing each signal pair in a shielded box through the mating interface.
Figure 1. GbX™ Mating Interface Cross Section
The multipair crosstalk is reported as voltage-induced, the worst-case victim pair in the grid with all neighboring pairs being simultaneously excited. In the case of GbX, the values include 11 simultaneously switching pairs.
Connector Crosstalk
Figure 2. Multiline, BXT
Reflective energy loss due to excessive connector reflections would be detrimental in a system. The measurements include the capacitive disruption of the vias and the connector. Connector impedance is measured on a time domain reflectometer (TDR) while mounted to a suitable set of test boards. Reflection is calculated from the peak values on the TDR in the connector region. Connector reflections are shown in Figure 3.
Figure 3. Connector Reflections
The via capacitive effect will be treated separately in the next section with measurements for both standard and tuned holes. The plated through hole performance is dependent on a number of variables, including ground plane clearance and card thickness.
Single Connector Test Vehicle
The GbX test fixture used to determine single connector performance was configured with eight mil, uncoupled transmission lines, standard board launch (0.0236" drill, 0.0356" pad, 0.0476" anti-pad), and a three-inch path length on both the daughtercard and the backplane. Laminate material was limited to FR-4 and a high-speed material with a loss tangent of approximately 0.004.
The geometry specific to various connectors influences the launch into the printed circuit boards (PCBs). The pin density and via diameter limit the maximum trace width that can route out of or through a footprint. For high-speed transmission, signal traces need an adequate cross section to limit copper losses. Compliant pin termination is the predominate method to terminate contacts in backplane systems due to the difficulty in uniformly soldering the large thermal mass of the backplane. (Also providing the ability for single pin repair.) The compliant pin boards were used in testing for this study, with both standard and varied ground plane clearances.
The maximum line width and spaces listed provide 100Ω differential impedance and are listed in Figure 4 for each family. Trace widths the test fixtures were .008" unless otherwise noted. Subsequent sections will vary line width.
Figure 4. Recommended PCB Routing
The standard plated through hole diameter for both connectors are also listed for compliant pin version of the connectors. For the GbX launch, the plated through hole capacitance is reduced by using an 0.018" compliant pin in conjunction with a special anti-pad. The capacitance can be further reduced by using various methods such as counter-boring or dual-density drilling. Some of these variations will be shown in the system test measurement section to follow.
The data on Figure 5 demonstrates connector performance at 2.5 Gbps through 12 Gbps. Single connector performance has been characterized by traditional methods such as reflections, crosstalk, and eye patterns. The measured data will be carried forward into the improved passive system.
Figure 5. Single Connector Eye Patterns
