Higher levels of the synchronous hierarchy are formed by byte-interleaving the payloads from a number N of STM–1 signals, then adding a transport overhead of size N times that of an STM–1 and filling it with new management data and pointer values as appropriate. STMs created in this way range upwards from STM–1 at 155.52 Mbps by integer multiples of four with no theoretical limit. For example, STM–16 is at 2,488.32 Mbps and can carry 16 x AU–4. STM–N is the generic term for these higher rate transmission modules.

All of the above processes are summarized for the full range of PDH rates supported by SDH, as shown in Figure 7. Other rates and future services are expected to be supported by concatenation. This is a technique that allows multiples of either lower- or higher-order VCs to be managed as if they were a single VC. For example, a VC–4–4c is a concatenation of 4 x VC–4, giving an equivalent circuit capacity of around 600 Mbps and is expected to be used for the transmission of ATM between major network nodes.

Figure 7. ITU–TS Multiplexing Structure

Before transmission, the STM–N signal has scrambling applied overall to randomize the bit sequence for improved transmission performance. A few bytes of overhead are left unscrambled to simplify subsequent demultiplexing. Broadband payloads such as ATM and IP are likely to occupy a large VC such as a VC–4, which when carried in STM–1 results in the SDH experiencing many successive bytes from each ATM cell. However, the unpredictable data patterns of ATM cells risk compromising the relatively short scrambler used in SDH. This could intermittently endanger the transmission of the whole SDH signal by affecting digit sequences and therefore the clock content needed for demultiplexing. For this reason, extra long scramblers are added for those payloads.