LVDS requires only a simple termination resistor, which can be integrated onto the chip. This costs much less than using multiple resistor and capacitor components for each transmission line. In addition, LVDS requires no termination or Vddq voltage supply, a big cost savings over technologies such as GTL, LVTTL, and stub series terminated logic (SSTL).
Because LVDS is capable of handling the high-speed data that results from serializing many parallel bits into a single data stream, LVDS chips commonly integrate serializers and deserializers. This saves about 50 percent of the cabling, connector, and PCB costs when compared to a parallel interconnect. The FPD–link chipset demonstrates this system cost savings. The chipset takes the 18- or 24-bit-wide red/green/blue (RGB) bus, and the VSYNC, HSYNC, and data enable control lines and multiplexes them down to only four or five pairs. This low-cost four- or five-pair link passes data through the hinge to the panel where it is demultiplexed. Typical interconnects range from about 8 cm to 40 cm in length and use low-cost flex circuit or twisted-pair cabling.
The final LVDS system benefit is its integration capability. Because it is possible to implement high-speed LVDS in a standard CMOS process, integrating complex digital functions with LVDS’s analog circuits is very beneficial. Integrating serializers and deserializers is only the beginning to mixed-signal LVDS chips.


