A significant advantage of LVDS technology is the lower power requirement. Figure 5 shows LVDS’s supply current remaining flat as the operating frequency increases, whereas the supply current for CMOS and GTL technology increases exponentially as frequency increases. LVDS benefits because it uses a constant-current line driver rather than a voltage-mode driver. The load power calculation (3.3 mA times the 330-mV drop across the 100-W termination resistor) means LVDS has only 1.1–mW load power consumption. By comparison, GTL consumes 40 mA of load current through a 1-V drop across the load resistor, which is a whopping 40–mW load power dissipation. LVDS also has low-power requirements compared to pseudo emitter coupled logic (PECL). The DS90C031 is an LVDS pin-compatible replacement part for the PECL 41L quad differential line driver. The LVDS part consumes 16 times less supply current than the PECL part (3 mA compared to 50 mA). Furthermore, the low power consumption inherent in LVDS technology eliminates the need for either heat sinks or special packaging. This benefit also reduces the system cost of Gigabit data transfers.

Figure 5. LVDS’s Supply Current Remains Flat as the Operating Frequency Increases

Another advantage of LVDS is its low electromagnetic-interference generation. The reasons LVDS generates low emissions are its low voltage swing, slow edge rates, the odd-mode differential signals, and the minimal I_cc spikes from constant current drivers. High-frequency signal transitions flowing through a transmission path create electromagnetic fields that radiate emissions. The field’s strength is proportional to the energy carried by the signal. By reducing the voltage swing and the current energy, LVDS minimizes these fields. However, even the reduced electromagnetic fields can cause radiation problems.