The simple phrase “Gigabits at milliwatts” conveniently describes the benefits of an LVDS system. These benefits are high-speed data throughput, power-miser operation, noise control, low cost, and higher integration.

LVDS system features, such as serializing data, encoding the clock, and low skew, all work together for higher performance. Skew is a big problem for sending parallel data and its clock across cables or PCB traces. The problem is that the phase relation of the data and clock can be lost as a result of different travel times through the link. However, the ability to serialize parallel data into a high-speed signal with embedded clock eliminates the skew problem. The problem disappears because the clock travels with the data over the same differential pair of wires. The receiver uses clock and data recovery to extract the embedded clock, which is phase-aligned to the data.

An example of LVDS’s high performance is the open LVDS display interface (OpenLDI) chipset that supports 24-bit color and provides throughput of over 5 Gbps using only eight data pairs and a clock pair (see Figure 3). The chipset serializes a 48-bit TTL interface down to the eight pairs and then deserializes it at the receiver. The chipset supports TTL clock rates of up to 112 MHz. To do this, each LVDS data channel serializes six TTL lines, plus a direct current (DC) balance bit, into a single high-speed LVDS pair. That pair operates at 784 Mbps with a data throughput of 672 Mbps. The OpenLDI chipset can also operate at TTL bit rates as low as 33 Mbps.

Figure 3. The OpenLDI Chipset Is an Example of LVDS’s High Performance

Besides giving tremendous throughput, the chipset reduces the interconnect width and provides other system benefits. The cable and connector are smaller and cost less; the cable is more flexible, and the connector has fewer pins. The beautiful eye pattern in Figure 4 is taken at the end of a 5-meter cable between the transmitter and receiver of the OpenLDI chipset. The transmitter drives a pseudo random bit sequence (PRBS) through the cable, and the receiver recovers the signal. The markers show the bit width to be 1.275 ns, indicating a data rate of 784 Mbps. Each of the 8 pairs carries this raw data rate, resulting in an aggregate bandwidth of almost 6.3 Gbps. This data rate includes overhead for DC balance, so the actual payload bandwidth is 5.38 Gbps.

Figure 4. Eye Pattern Measured at the End of a 5-Meter Cable between the Transmitter and Receiver of the OpenLDI Chipset