PDF of this tutorialLow-voltage signals have many advantages, including fast bit rates, lower power, and better noise performance. Design engineers have previously used full-swing CMOS and low-voltage, transistor-transistor logic (LVTTL), but as bit rates increase, these solutions become unattractive. More recently, designers have turned to reduced-swing technologies such as stub series terminated logic (SSTL) and gunning transceiver logic (GTL) to gain speed, save power, and reduce noise. LVDS increases these advantages by lowering voltage swings to about 300 mV. To increase noise immunity and noise margins even further, LVDS uses differential data transmission. Differential signals are immune to common-mode noise, the primary source of system noise. Because its voltage change between logic states is only 300 mV, LVDS can change states very fast. An LVDS signal also changes voltage levels without a fast slew rate. Slowing the transition rate decreases the radiated field strength. Slower transitions reduce the problem of reflections from transmission-path impedance discontinuities, decreasing emissions and crosstalk problems. Low-voltage swing reduces power consumption because it lowers the voltage across the termination resistors and lowers the overall power dissipation.
Figure 2 emphasizes the advantage of a low-voltage swing for higher performance. For example, when the signal level changes 300 mV in 333 ps, the slew rate is only 0.9 V/ns, which is less than the 1 V/ns benchmark slew rate commonly acceptable for minimizing signal distortion and crosstalk. If you use the old benchmark that rise and fall times should be no more than two-thirds of the bit width, then signals with 333-ps transitions can operate as high as 1 Gbps with plenty of margin.
Figure 2. The Lowered Voltage Swing Maintains High Speed without Excessive Slew Rate
