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Low-Voltage Differential Signaling (LVDS)

Table of Contents:
Definition and Overview
1. Introduction
2. LVDS Physical Layer
3. Multiple Technologies and Supply Voltages
4. Gigabits at Milliwatts
5. Flat Supply Current versus Operating Frequency
6. Low Electromagnetic Interference
7. Cost Benefits
8. Many Channels per Chip
9. DC Balance for Longer Cables
Self-Test
Glossary
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Self-Test
1. Even though data is digital, designers are choosing analog LVDS to drive transmission lines.
a. true
b. false
2. Moving information between systems is the main use for LVDS solutions today.
a. true
b. false
3. An LVDS signal is immune to common-mode noise.
a. true
b. false
4. Which of the following does not accurately describe LVDS?
a. high-speed data throughput
b. high cost
c. higher integration
d. power-miser operation
5. LVDS has ______________ power requirements compared to PECL and GTL.
a. lower
b. higher
6. The input differential signal amplitude is undisturbed when noise appears ___________________.
a. more at the minus input
b. more at the plus input
c. commonly to both inputs
7. LVDS technology has better EMI performance than all other interface technologies.
a. true
b. false
8. Even with LVDS, it is not possible to integrate multiple channels per chip.
a. true
b. false
9. The single-bit transition cannot overcome the intersymbol interference at the end of the cable when ____________________.
a. the disparity magnitude is small
b. the disparity magnitude is large
10. The _______________ LVDS data bit indicates whether the data in the payload is true or inverted.
a. fifth
b. sixth
c. seventh
d. eighth
Glossary >>

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