Triggering on a transaction type alone or with an address does not dramatically challenge today’s advanced trigger systems. As shown in the bus operation outlined earlier, a new transaction begins by asserting the ADS# signal. When this occurs, the logic analyzer must sample the transaction type from the REQ lines and the address from the ADDR lines. If the logic analyzer detects that all three events have occurred (ADS# = 0, Transaction Type = I/O Write, and Address matches the desired one), then it triggers. Otherwise it continues looking for this combination of events. This sequence is diagrammed in Figure 4.

Figure 4. Flowchart for Triggering on a Transaction Type with Address

For a complex bus with pipelining, a more complex trigger sequence is required to capture I/O writes to a specific port (Figure 5). This complex trigger introduces the concept of multiway branching, available on many modern logic analyzers. As each section is discussed, the intimidating flowchart becomes more understandable. As we desire to capture only I/O writes, we assume the trigger system has the ability to store nothing globally. During each step, we will store samples and override this feature so that the display contains only I/O writes. Note the absence of a trigger point for this sequence. As it is capture only, we will need to press the STOP button to end the trace. As shown in the subsequent trigger example, a trigger point can easily be added.

Figure 5. Flowchart for Capturing I/O Writes to a Specific Port on a Complex Bus with Pipelining