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Triggering a Logic Analyzer on Complex Computer Buses
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Agilent Technologies

3. P6 Family As Example
To show some logic analyzer triggering techniques for a complex bus, the operation of the P6-family system bus is briefly described for various pipelined and deferred response techniques. This bus is extremely complex and would take pages to cover in detail. For further details, refer to the Intel P6 Family of Processors Hardware Developers Manual (order number 244011-011), available on Intel’s Web site at http://www.intel.com or the MindShare Pentium Pro and Pentium II System Architecture book (ISBN 0-201-30973-4).

Figure 3 shows the behavior of the queue depth (RCNT), address, request, data, response, and other lines during a series of transactions. The diagram begins with the yellow transaction on an idle (RCNT= 0). Simply asserting address strobe (ADS) increments the queue depth on the next clock cycle (RCNT=1). After passing the required phases (error and snoop), the agent responsible for responding to the yellow request defers the response by asserting DEFER and indicating it on the response signals. Before completion of the yellow transaction, however, the next transaction (green) arbitrated and finished its request phase. The beginning of the green transaction increments the queue depth again, but it decrements to RCNT=1 one clock after the completion of the yellow transaction. Watching the queue depth increment and decrement on subsequent transactions shows that it is based on the number of outstanding transactions on the bus. As the queue depth increments, responses must come back in order, so it is called an IOQ. This implies that even if the red transaction had a response immediately, it must wait for the green one to finish first. This is an important concept for the trigger example described later. In this example, the blue phase happens to be the deferred reply to the yellow transaction (indicated here by the *). Note how instead of the yellow request agent retrying the entire transaction, the reply agent simply arbitrates and transfers the necessary data. (A deferred reply is typically much farther apart than two states.)


Figure 3. A Simplified View of the Bus Operation

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