These complex bus operations rely on dividing bus operations into different transactions. Early in a transfer, a transaction type identifies the intent of a device using the bus. This enables intelligent recipients to begin processing before an entire transfer is complete. Transactions can be partitioned into discrete logical chunks or phases with a defined end phase. Each bus architecture can define its own set of phases. The phases for the P6 family of processors are shown in Figure 2. Multiplexing, bursting, and pipelining all use transactions as a foundation.

Figure 2. The Many Bus Phases of the P6 Family of Processors

A burst data transfer is a more efficient way to move a chunk of data than a series of simple data write transactions. A data sender begins by announcing its intent to do a write and giving a start location. After this setup occurs, it begins inundating the receiver with data. Because the receiver has already acknowledged the start location, it then takes the responsibility of tracking the continued destination of the data. This is typically accomplished by incrementing an address counter on the word size. The bus is thereby emancipated from the tedious task of providing a destination for every data transfer, greatly reducing overhead work. An example of a transaction-based bus that allows bursting is the PCI bus. After the sender provides the start location (address) of a read or write, the data is sent continually across the bus. Control signals dictate the start and end of the level, while the receiver is tasked with incrementing the address counter and placing the data in the proper location.

The P6 family of processors resembles many other sophisticated buses in use today. This architecture introduced an eight-stage pipeline that enables much higher utilization of the electrical traces on the motherboard. A deferred-response transaction was added to the P6-family system bus architecture, adding a new and highly desirable dimension to the bus. Many microprocessor vendors use different permutations of these bus-architecture elements in the processor front-side bus.

Pipelining or queuing of actions not only allows a device to begin work on a transaction before it is complete, it actually allows for another transaction to begin before its predecessor is complete. This is physically accomplished by defining a certain group of signals that can only be used for one phase of each transaction. Once the phase is over for one transaction, another transaction is free to use those signals. As there is less latency between the beginning of different actions, there is higher bandwidth. In the P6-family system bus architecture, the pipeline is tracked by devices on the bus using an in-order queue (IOQ).

Deferred response is the ability of any bus agent to communicate, "Hey, I’m not ready yet. Go do something else, and I’ll get back to you when I’ve got what you asked for." This simple concept dramatically decreases bus idle time, while increasing bus complexity.