During the early days of microprocessor-based computer systems, adequate performance was achieved by nonpipelined, nonburst, and nontransaction-based buses. These buses had a very simple protocol with address, data, and a set of control signals all present at the input when a clock edge arrived. Wait states were often added to the bus while it waited for the target to respond. As processors became exponentially faster than the buses that carried the information to them, the bus remained idle for even longer. The latency created by this scenario became an extreme system bottleneck.

Designers soon realized that there was a variety of ways to increase bus bandwidth. Increasing the number of data signals proved to be one simple way to increase bandwidth. Growth in this area continues, but other methods to increase bandwidth have also been introduced. One of these methods is separating the location (address), intent (transaction type), and relevant information (data). This separation allows for streaming data (bursting), reusing signal lines (multiplexing), and even overlapping signals (pipelining). These techniques result in bus performance that has reasonably kept pace with microprocessor technology.

Pipeline and transaction-based buses are used in many common applications today. The proliferation of different bus architectures partially resulted from the separation of processor, I/O, graphics, and memory buses. Nearly all computers on desktops today have a variety of transaction or pipelined buses, as shown in Figure 1. The processor front-side bus (FSB), the peripheral component interconnect (PCI) bus, and the accelerated graphics port (AGP) are just some examples from a typical system. Intel began using advanced buses early in the x86 architecture. Motorola began its continued use of pipelined buses with the PowerPC. Even the low-power newcomer, ARM, has implemented a pipeline in its processor bus family. Each of these buses is different, but they all contain the same basic transactional elements and pipelining architecture that present challenges to a logic analyzer and its users.

Figure 1. Modern Systems Often Have a Variety of Transaction or Pipelined Buses