PDF of this tutorialOne of the principal innovations of the CompactPCI standard is its introduction of hot swappability (hot swap) to CTI products. This, combined with effective simplicity and interoperability, explains the widespread appeal of the technology.
Up until this point in time, hot swap has been an asset demanded by telcos that simply could not be delivered by suppliers of PC–based CTI solutions. Available on VME in a complex implementation and not to an open standard, previous solutions have been costly and manufacturer specific. It was believed that the barrier between hot-swap and PC–based CTI solutions was unbridgeable. Now, however, CompactPCI allows true fault tolerance and security to be achieved through low cost, manageable solutions.
All large, central office (CO)–type switches are expected to have hot swappability to permit the kind of fault-tolerant architecture and reliability the telecommunications industry demands. At a stroke, CTI applications gain long-denied credibility throughout the industry.
Hot swappability or live insertion is defined as the ability to insert or remove a process card from a live system. This process places several requirements on the developer. Firstly, the procedure must be safe; a live system is, by definition, one that requires power to run an application process. Secondly, the removal or insertion of a card into the system must not cause any disruption to the ongoing processes of the application, such as switch failure. Thirdly, taking the card in and out of the system must not itself be affected by this action. Although the requirements are straightforward, they have been impossible to achieve using standard PC architectures. How, then, does CompactPCI resolve this problem?
In fact, the hot-swap standard generated by PICMG known as PICMG 2.1, announced in July 1998, is relatively simple and defines a manual procedure by which hot swap can be achieved. The procedure involves hardware and software processes linked to electrical signals and can be implemented by all manufacturers, provided that they follow the appropriate guidelines.
The procedure is dependent on several key factors. First, the silicon chips utilized by the PCI–bus architecture must be able to communicate directly with each other, not via the mediation of hardware buffers. The chips achieve a state in which their signals can be synchronized with those of the backplane. Because nothing exists between the two, synchronization may occur quickly, although the lack of mediation buffers means that the electrical loading of the bus must be precisely monitored to maintain a synchronous state.
Second, the pin connectors between the CompactPCI card and the mating contacts on the CompactPCI bus are designed to be of variable length. Given this situation, certain pins will make contact with their respective mate before others do or, conversely, lose contact before others do so. Finally, each card is secured in place via a lever that clips into position at the front or rear of the chassis unit.
The procedure essentially follows a predictable sequence. When a card is selected for extraction, the lever is raised or released. This action breaks a contact on some associated circuitry and sends a signal to the controlling software, which, in turn, signals that a particular card is being prepared for extraction. Hence, the system can redirect processes elsewhere. Once the withdrawal process begins, certain pins will lose contact with their mates before others. In fact, there are three lengths defined by the standard. The shortest will obviously lose contact first, which sends a signal to the control system indicating that the card is being removed. Thus, power-down procedures can be initiated.
When a card is being inserted, the longest pins make contact first, thereby generating a signal that instructs the system to begin delivering power to the card. As the shortest make contact, further signals are generated that inform the system that the board is now fully in place and that all of the power-up procedures can be completed. The medium-length pins make contact as the initial charges are being applied to the card, and the PCI chip resumes operation. Closure of the security lever completes the process.
The PICMG specification defines the signals associated with each event that developers use to build hot swappability into their applications. This activity demands close monitoring at a high level to ensure that any applications in service take all necessary actions to divert resources away from the removed card or to allocate resources to an inserted card. Thus, developers must be extremely diligent.
A further consideration involves timing. All telecommunications systems are either synchronized to an external clock source or generate a clock source that must be distributed to other equipment via the telecommunications network. Telecommunications equipment does not usually accommodate several clock sources. If the card to be removed is the card that is responsible for distributing the timing signal across the system, synchronization may be lost, causing the system to run free. However, the CompactPCI bus enables the reception of two timing signals. Hence, if one source is lost, a secondary source can be provided to ensure that the system remains appropriately synchronized.
In mission-critical systems such as those experienced in the telecommunications industry, such capabilities have great importance, and their availability in such systems will undoubtedly prove to be revolutionary.
