PDF of this tutorialCompactPCI cards can come in two different sizes (3U or 6U), but the standard defines a common physical design. There are a number of physical connectors utilized to support integration to the physical bus itself. Although different connectors are used in each version due to size discrepancies, each connector serves a specific purpose and contains a specific number of 2-mm pins (535 in all). The standard for pin connectivity was originally developed by Siemens and confers several advantages:
- power and grounding access
- high signal integrity
- minimal noise loss
- minimal noise susceptibility
This rigid definition is in contrast with the multiplicity of arrangements that have existed in previous systems and further assists the interoperability of the standard (see Figure 1).
Figure 1. Rigid Definition
There are five connectors in total. J1 always acts as the 32-bit PCI bus interface. This is used by both the 3U and 6U board versions. J3, J4, and J5 are allocated for input and output signal distribution and, amongst them, offer a total of 315 2-mm connector pins. They are not present on 3U–card varieties. J2 offers an additional 32-bit bus interface as an option. Hence, when it is utilized, a total bus of 64-bits is available. Taken together, J1 and J2 constitute the CompactPCI bus and J3, J4, and J5 constitute the local or subbus. The subbus may itself be broken down, given that J4 specifically provides access to the H.110 bus, while J5 provides access to other external input and output signals. J5 will be explored in more detail in subsequent sections.
This subbus enables multiple boards to communicate with each other quickly and efficiently. In telephony applications, this is particularly important, as it allows rapid transfer of data between cards in a system. Furthermore, the simplicity of design is in contrast to the complexity of ISA or VME systems (see Figure 2).
Figure 2. Simplicity of Design
In addition to the allocation of connectors to the computer telephony and CompactPCI buses, specifications also require the addition of mezzanine-type daughter boards to individual CompactPCI cards. This allows CompactPCI cards to support higher processor or chip density to host DSP chips for advanced telephony applications.
Associated with the connector design, the Institute of Electrical and Electronic Engineers (IEEE) specification 1101.11, known as rear panel–transition module, has been incorporated into the CompactPCI standard. This standard requires permanent or semipermanent connectivity of inputs and outputs and gives mechanical definition to the strong grounding and shielding practices of electrical components. This is particularly important when one considers the demanding electromagnetic capability (EMC) and safety legislation now enforced by governments around the world.
The CompactPCI specification also provides a mechanism that identifies the physical position of each card and maps it into software. Thus, any one card has knowledge of the inputs and outputs, internal and physical, to which it is connected (assuming that the software is correct). Specification 1101.11 also permits specific slots to be assigned to specific cards, should this be a requirement.
At present, the physical capacity of the CompactPCI bus is limited. It can support up to eight cards, which, if one is designated the CPU, leaves seven slots free for peripheral cards. Because CompactPCI's tremendous potential for telecommunications applications was soon recognized, a standard that specifically defines how CompactPCI systems should use the H.110 bus was originated. Known as the computer telephony specification or PICMG 2.5, it complements other CompactPCI specifications. Theoretically, this standard enables up to sixteen E1 or T1 PCMs to be terminated on a single CompactPCI card. It also suggests that up to twenty slots could be available in a single chassis, which would have the net result of allowing 320 E1 or T1s to be switched in a single unit. The largest ISA–based systems could only support thirty-two E1 or T1 terminations in a single chassis.
Although such a scenario is not presently possible, it does serve as an indication of the tremendous potential of CompactPCI to permit the design of high-density applications at low cost. However, work is underway in providing physical bridges between each CompactPCI cluster of eight cards. Such systems would combine multiple clusters in a single chassis.
A final consideration for capacity is the switching bandwidth of the H.110 CT bus itself. This has a maximum capacity of 4096 bidirectional timeslots, each with a capacity of 64 kbps. In other words, 2048 duplex call paths may be established across a single H.110 bus. This bus acts a time-division multiplexer (TDM) by supporting the transmission of various kinds of signals over the same transmission medium.
It is clear that CompactPCI offers a switching solution of great power. How that power can be realized is the subject of Topic 5.
