To evaluate back drilled via structures, various reliability testing sequences applicable to PCB vias were performed in accordance with the Telcordia GR-1217-Core and GR-2969-Core requirements for telecommunication hardware. The test plan includes bare board sequences and testing to evaluate press fit termination. This testing has been performed to quality level III. In addition, to the reliability testing, temperature rise and solder shock testing was also performed. Vias were evaluated both with and without anchoring pads at the bottom of the plated hole or back drilled end of the via (Figure 16). See Figure 17 for test vehicle layout.

Hole Sizes: 0.018" and 0.022" Thickness: 0.260" Layers: 26 Material: FR-4 Size: 8" x 10"

The following reliability test groups were chosen to assess the plated through hole integrity:

1. Compliant Pin Performance
2. Current Rating
3. DWV dielectric withstanding voltage
4-6. Humidity cycling and thermal shock
7. Mixed flowing gas
8. Electro-migration

The humidity cycling and thermal shock group was chosen to evaluate the effects of thermally stressing the via structure in order to look for de-lamination between the copper plating and the drilled hole. The mixed flowing gas group was performed to accelerate the corrosion rate between the compliant pin interface and the plated through hole. The purpose of the electro-migration group was to analyze the metallic material growth between the plated through hole and the exposed copper layers. The compliant pin performance testing was performed to mechanically stress the via structure and to evaluate the performance of the compliant pin. The purpose of mechanically stressing the via structure was to see if the copper hole would de-laminate from the drilled hole wall. A portion of that particular group was also tested to failure, meaning that the pins were purposely pushed through the hole to try to cause the copper to de-laminate. Since back drilling removes copper from the via, the current rating of the via was also tested to evaluate the current capacity. All of the test vehicles had two different via structures, one with anchoring pads and the other without anchoring pads to evaluate the mechanical stability of the via structure. Groups 1 and 4 -6 also had three compliant pin repairs prior to submitting to testing. Figures 18 through 26, below, show the results of the testing:

Mechanical Reliability Test Groups (figure 18)

Figure 18: Group 1 Results: Compliant Pin Insertion - Retention (figure 19)

• Compliant pin performance testing showed no adverse effects on the backdrilled hole after three insertions and retentions
• 88 insertion data point
• 66 retention datapoints

Figure 19: Compliant pin insertion - retention force Group 2 Results: Temperature Rise (figure 20)

Reliability Test Plan (figure 21)

Group 4 - 6 Results: Thermal Shock and Humidity Cycling

• Resistance change, Thermal Shock and Humidity Cycling, Groups 4-6
• Group 4- First Insertion
• Group 5- Second Insertion
• Group 6- Third Insertion
• No values beyond 1milliohm change
• 650 Data Points

Figure 23 Group 7 Results: Mixed Flowing Gas (figure 24)

• Resistance change, 10 Days Mixed Flowing Gas with thermal conditioning, Group 7
• No values beyond 1milliohm change
• 264 Data Points

Figure 24: Mixed Flowing Gas Group 8 Results: Electro-Migration

• 500 Hours, 10 Volt Bias
• Spec Requirement: Bellcore 1000 Mohms Minimum
• Results: 15,000 Mohms

As shown, all groups passed testing per stated requirements. Group 9 also passed, although the intent for these configurations was to stress the hole and not to imply this configuration be used in application.

Group 9 Results: Additional Testing

• Solder Shock per IPC-TM-650
• Over Pinning
• Reverse Pinning

Figure 25

Conclusions:

The technique of back drilling is being used in production today to tune the characteristics of a plated through hole in a printed circuit board. The decision of when to back drill depends primarily on the signal frequency content and the length of the stub.

Although efforts to reduce stub effect can be accomplished through various techniques such as using lower dielectric material to reduce thickness or routing high speed signals to the bottom of the board, eventually higher frequency designs and increased board thickness will force some treatment of the stub. It is also important to remember that the package or connector is critical to the signal path but independent of the stub effect, and for this reason changing the termination from press fit to SMT may not resolve the inherent signal loss.

Looking forward, an on-going effort will be required on seamless implementation of the design rules, evaluating the electrical and reliability effects of plated through hole used in an SMT application, and further refining the design rules based on other structures.

References:

• Transmission Line Design Handbook - Brian Wadell
• ISBN 0-89006-436-9

© Teradyne, Inc. 2003-2004