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Practical Guidelines for the Implementation of Back Drilling Plated Through Hole Vias in Multi-gigabit Board Applications
Sponsored by:
Teradyne-x

3. Bare Board Fabrication Process
As discussed previously, back drilling, or controlled depth counter boring, is a process where plating is removed from the unused portion of the via. Multi-layer printed wiring boards are processed in a standard manner, adding a secondary drilling operation after plating using PWB CNC drilling equipment with controlled depth enhancements. CNC drill files created from customer data allow this process to be automated and repeatable.

Over Drill Diameter: One important parameter is the secondary drill diameter. This drill diameter must be greater in diameter than the primary drill to allow removal of all the electrodeposited plated metal, typically copper with an additional surface finish. Minimization of this diameter is important to avoid reduction of routing channels which compromise hole to trace spacing in the pin fields. A controlled experiment was done varying the over drill diameter to 5, 7, 10 and 13 mils above original drill size to determine the presence of residual plating. Ten holes from each corner of 4 panels drilled on 4 spindles in one pass were cross-sectioned and evaluated for complete plating removal and internal spacing. No residual plating or spacing violations were observed on any over drill hole size. The current recommendation is 7 mils over original drill diameter.

Backdrill Depth: Back drilling is a trade off between manufacturing cost and electrical performance. Contributors to back drill depth variation have been characterized which affect yield and cost. An optimized setup process achieves a 3 sigma overall variation of +/- 5 mils to nominal target depth. This comes from two components: mechanical depth and layer position. At least a 10mil target nominal depth before the last layer connected is recommended.


Bare Board Reliability Testing: A forced failure designed experiment was conducted, intentionally varying process parameters, which took the PTH integrity to extremes. Parameters varied were drill hole quality, electroless copper etch back rate, and copper plating thickness (Figure 13). Test vehicles were subjected to thermal cycling and 6x solder shock testing. As expected, no failures were observed on either normal PTHs or back drilled PTHs on boards processed under standard conditions. Failures due to cracking were observed on both hole types exhibiting poor drilled hole quality and thin copper plating conditions.



Figure 14a: Backplane Signal Pin Insertion Force vs. Finished Hole Size


Figure 14b: Backplane Signal Pin Retention Force vs. Finished Hole Size

Cost Model: A cost model factors in set up time, run time, and drill bit cost. Application of this model to various board designs results in an average increase of 7% added to the bare board price. For example, a typical board requiring fifteen hundred backdrilled holes would result in an additional cost of about $50 per board (Figure 15).


Figure 15: Back drilling Costing Examples

Surface Finishes and Exposed Cu: For electrolytic deposited surface finishes (re-flowed PbSn, Gold) Teradyne currently would perform back drilling after that process, resulting in exposed copper at the end of the stub. Back drilling can be done before immersion surface finishes, resulting in no exposed bare copper at the end of the stub. Immersion tin for backdrilled backplanes is preferred.

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