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Practical Guidelines for the Implementation of Back Drilling Plated Through Hole Vias in Multi-gigabit Board Applications
Sponsored by:
Table of Contents:
Definition and Overview
1. Back Drilling: Background
2. Electrical Effects
3. Bare Board Fabrication Process
4. Assembly Level Reliability Verification Testing
Self-Test
Glossary
PDF of this tutorial
Self-Test
1. The unused portion of the Plated Through Hole is sometimes referred to as a resonant stub.
a. True
b. False
2. Notch frequency can be effected by
a. increasing the anti-pad diameter
b. changing the board laminate material
c. via stub length
d. all of the above
3. By changing to a laminate with a lower dielectric constant, you will have a larger effect on notch frequency due to the reduced _______________
a. dialetric loss
b. board thickness
c. impedence
d. PTH diameter
4. The stub notch frequency is primarily a function of its ________.
a. length
b. width (or “Q”)
c. geometry
d. material
5. Relatively small increments in stub length have no measurable effect on moving F
f
.
a. True
b. False
6. A recommended secondary drill diameter is ____ over original drill diameter to completely remove residual plating and achieve desired hole to trace (internal) spacing in the pin fields.
a. 5 mils
b. 7 mils
c. 10 mils
d. 13 mils
7. Process parameters for bareboard reliability testing do NOT include:
a. Drill Hole Quality
b. Electroless Copper etch back Rate
c. Copper Plating Thickness
d. Drill Hole Size
8. During verification testing, the _________________ accelerated the corrosion rate between the compliant pin interface and the plated through hole.
a. humidity cycling group
b. thermal shock group
c. mixed flowing gas group
d. electro-migration group
Glossary >>
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