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Practical Guidelines for the Implementation of Back Drilling Plated Through Hole Vias in Multi-gigabit Board Applications
Sponsored by:
Teradyne-x

Introduction

A. Definition
This tutorial will focus on practical guidelines for the implementation of back drilling plated through-hole (PTH) vias in multi-gigabit board applications.

B. Tutorial Overview
In copper board-to-board applications, data rates of 2.5 Gb/s are common. Recently there have been numerous efforts to boost single channel data rates to and beyond the 10 Gb/s range. These channels can be broken into segments comprised of the device, package effects, board laminate material, high-speed connectors, and the launches into and back out of the interior layers of the printed circuit boards or plated through holes. This paper will focus on the PCB launch, specifically a technique referred to as back drilling. Electrical measurements, long-term reliability testing and process implications will be reviewed and preliminary design guidelines will be presented.

Transport data rates of 3.125 Gb/s are now commonplace in board-to-board applications. As data rates increase to 5, 6.25 or 10 Gb/s the entire channel topography will need to be re-examined. A typical channel includes signal traces, connectors, and plated through hole vias. New connectors are entering the market with better impedance matching and improved shielding techniques to accommodate the sharper rise times associated with the faster data rates. Likewise, laminate suppliers continue to develop new board materials with lower loss tangents to reduce the signal attenuation due to laminate loss. Using equalization circuits and signal pre-emphasis, device suppliers are driving solutions to improve signal fiedlity at increased data rates.

A piece of the transmission path which cannot be neglected, is the plated through hole or via. Plated through holes, or PTHs, are a means to transport signals into interior layers of a multi layer PC board. PTH vias are used in this way under the pad array of the device package, and in the launch of separable connector interface into boards. The PTH is common to various device packages such as a ball grid array (BGA) and connector types including press fit and surface mount right angle board to board, mezzanine and cable connectors. In the case of a typical backplane system (see Overview Figure A), the signal passes through at least size vias or PTHs while traveling from driver to receiver.


Overview Figure A - Typical Signal Path

The PTH portion of the signal path becomes more "visible" to the signal as increased frequency content is needed to produce sharp rise and fall times of the digital pulse. The focus of this paper will be on a technique commonly referred to as back drilling, or counter boring, of the printed circuit board PTH. Included in this study will be the electrical effect, the process implications (including a cost model) and results of long term reliability testing.


Overview Figure B - Back drilling of printed circuit board

C. Back drilling Modules

  • Back drilling background
  • Electrical Effects
  • Process Implications
  • Reliability Testing

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