PDF of this tutorialATM is primarily a transport-level protocol. ATM systems operate by establishing a connection between two users and then sending data using the unique ATM cell format. The primary issues for ATM layer testing are to test the equipment function and measure system performance when transporting ATM cells between any two points across a network connection.
An ATM Network Contains Buffers
Each ATM cell can pass through one or several ATM switches during end-to-end transmission (shown in Figure 1). Cells can be processed through buffers (queues) in ATM switches introducing variable delays to the ATM cell traffic throughout the entire ATM network. The cell delay through switch buffers is dependent on the aggregate traffic loading on the network. Switch buffers can also become overloaded and cause a loss of cells.
Figure 1. All ATM Switches in the Network Can Buffer Cell
Different Queues for Each ATM Service Category
Each ATM switch may implement a different queuing mechanism. The queuing mechanism may be simple or extremely complex depending on the types of ATM service categories supported by the switch (i.e., UBR or ABR). This design may cause cells belonging to different ATM service categories to be processed through different queues in the ATM switch. Even within a single ATM service category (i.e., UBR), different virtual channel connections (VCCs) may be processed through separate queues. These advanced cell scheduling mechanisms introduce a high degree of complexity to the ATM switches and require extensive testing.
Figure 2. An ATM Switch May Have Queues, Shapers, and Complex Scheduling Mechanisms
(Click on image for full-size version.)
ATM switches may also perform shaping of its output cell traffic. This introduces another form of cell delay called jitter. The switch matrix design may include several layers (one for each ATM service category) and this delay may result in cell loss or cell misinsertion (in rare cases).
Switch to VCI/VPI Translation
One of the major ATM layer functions of an ATM switch is to perform virtual channel identifier (VCI)/virtual path identifier (VPI) translation from the input to the output. This function is achieved using an address lookup table that is programmable through signaling set-up messages or via network management. Cell misrouting and cell misinsertion can occur if the address translation function does not operate correctly.
Methods to Test the ATM Layer
Quality of service (QoS) tests are performed under out-of-service conditions. Testing of the ATM layer requires an ATM analyzer capable of generating ATM traffic and then monitoring the same traffic to make specific measurements.
The ATM analyzer traffic generator must be capable of transmitting cell streams at full line rate to stress test ATM switches and devices. It should also allow selection of channels from a range of available virtual channels (VCs) on the link under test and adjustment of the cell transmission rate and background traffic conditions. These different channels are then mixed together to emulate real-world traffic to ensure that the switch can simultaneously process traffic for different ATM service categories.
Figure 3. Creating a Mix of Traffic
QoS Parameters
Use of the ITU defined O.191 test cell (Figure 4) provides the most accurate method to calculate ATM–layer performance parameters. The primary advantage of using the O.191 test cell is that measurements are interpreted in a consistent manner:
- Standardized format enables monitors to distinguish between cell errors and cell misinsertions.
- 10–ns time stamp resolution in the O.191 test cell allows accurate timing for existing rates and migration to very high bandwidths (OC–12 and higher).
- Scrambling of the test cell payload effectively alters the bit patterns so that the O.191 cell stream acts like a pseudo-random bit stream (PRBS).
- The large test cell sequence number allows cell loss measurements to be taken over extended periods of testing. This is of particular importance when testing for large bursts of cell losses as often occurs in real-life networks.
Figure 4. ITU O.191 Test Cell
The following ATM layer statistics are significant for measuring ATM QoS:
- minimum cell transfer delay (CTD)—minimum round-trip time for transmitted (foreground) test cells
- maximum CTD—maximum round-trip time for transmitted (foreground) test cells
- mean CTD—average round-trip time for transmitted (foreground) test cells
- peak-to-peak cell delay variation (CDV)—difference between maximum and minimum (foreground) test cell delay; this is generally a good first estimate of the cell delay variation tolerance (CDVT) for the network
- CDV distribution—histogram indicating the number of foreground test cells detected having a CTD within a specified range, monitored over specified sampling time intervals during the test period
- cell loss and cell loss ratio (CLR)—measurement of the difference between the number of foreground test cells transmitted and the number of test cells received
- cell sequence integrity—identifies any out-of-sequence cells by comparing the sequence of received foreground test cells with the transmitted test cells; this is a severe error that should cause immediate notification to the user.
- cell error and cell error ratio (CER)—the number of foreground test cells received with single or multiple payload bit errors divided by the total number of transmitted test cells
- cell misinsertion and cell misinsertion rate (CMR)—CMR is the number of cells detected on one VC having payload information belonging to another VC; this test provides a good indication that network equipment is overloaded or is reconfiguring and is misrouting or mis-multicasting cells. Note that CMR is calculated as a rate (not a ratio) since CMR is independent of ATM traffic load.
Network Impairment
A valuable feature for ATM layer testing is the ability to introduce controlled impairments into a live ATM network—directly affecting the network QoS levels. This allows the ATM terminal vendors or ATM terminal purchasers to verify equipment operation under worst-case conditions (with cell losses, cell delays, bit errors, etc.).
GCRA Algorithm
All ATM switches perform user parameter control (UPC) verification on received traffic. The UPC function is based on the general cell rate algorithm (GCRA) (i, l)—algorithms defined in the ATM Forum and ITU standards. The UPC is a very critical function of switch behavior verifying that all sources obey their specific traffic contracts.
The UPC function in switches is performed primarily in hardware. Switch designers may implement hardware features that make assumptions about existing traffic conditions and implement shortcuts. For this reason, it is very important that the test equipment can verify the correct operation of the UPC function.
Figure 5. Illustration of the GCRA (i,l) Algorithm as Leaky Bucket
The ATM test analyzer should be capable of generating traffic that obeys source description as well as introducing violations to the negotiated GCRA contract.
OAM Parameters
Operation and maintenance (OAM) cells are used for alarm surveillance, performance monitoring, and troubleshooting. The OAM cells consist of five flow levels (F1–F5) where the highest (F4–F5) are dedicated to the ATM layer. All layers are interrelated as shown in Figure 6. Alarms in the lower layer move upwards to the higher layers.
The OAM cell traffic is transmitted intermixed with the user cells on each channel. An ATM test analyzer should be capable of sending and receiving OAM cells as well as generating the lower-layer OAM signals to properly test the complete OAM functionality.
Figure 6. OAM Hierarchy
(Click on image for full-size version.)
