Vice President, Design for Manufacturing
Abstract
With nanometer process technologies at 130nm and below, semiconductors exhibit effects that could be safely ignored in earlier process generations. Today, advanced processes bring a range of physical and electrical effects that can degrade circuit performance well beyond the remedies of traditional yield-enhancing practices performed after tape-out. Increasingly, the ability to optimize yield depends on development strategies able to account for the constraints and opportunities of advanced manufacturing on a design-specific basis. The availability of manufacturing-aware tools and methods enables semiconductor manufacturers to enhance yield by bringing manufacturing concerns more effectively into earlier stages of design. This white paper discusses the key factors affecting yield in nanometer process technologies and describes the increasingly significant role that design plays in enhancing yield in nanometer circuits.
Introduction
For integrated circuit (IC) manufacturers, each new generation of process technology has exacerbated the difficulty of achieving acceptable silicon performance (see Figure 1). At 0.18um and larger geometries, design yield was predictable and within acceptable margins. Designers worked with a relatively stable set of process metrics, relying on manufacturing to find incremental yield improvements as designs ramped to volume production. In turn, the post-design ramp to volume production was relatively steep (see Figure 2a), and when yield dropped below expected levels, engineers could likely fix problems after tape-out.
Advanced nanometer process technologies introduce physical and electrical effects that dramatically increase the risk of silicon failures using conventional development methodologies.
At 0.18um and above, semiconductor companies could count on a rapid ramp to volume (A). For nanometer nodes, development approaches that proved successful for earlier technologies fail to predict silicon performance, causing yield ramps to flatten (B).
As process geometries shrink below 130nm, however, manufacturers face greater difficulty in achieving predictable silicon performance, so actual yield remains flat in the early stages of production ramp-up (see Figure 2b). In fact, manufacturers find that only slightly more than 40% of nanometer designs operate as expected and more than 60% need a complete mask re-spin to achieve acceptable yield and performance.
Even as manufacturers face lower silicon success rates, the cost of failure continues to rise dramatically. In terms of direct costs alone, design respins are becoming significantly more expensive. For example, a semiconductor company creating a typical 130nm device spent US$10M or more in design costs with another US$750K to US$1M in mask costs. At the 90nm node, mask sets alone jump by 25% to 50%. Worse, a slower ramp to yield reduces time-to-profit and even final revenue, because delayed entry means fewer sales in today's environment, where fast-changing demand abbreviates product life cycles and shortens market windows.
Advanced manufacturing brings diverse new factors that impact yield, broadening in turn the scope of development efforts required to maximize yield. Indeed, the notion of yield enhancement itself expands with emerging nanometer designs, outpacing the ability of traditional manufacturing-oriented methods to realize the full potential of advanced nanometer technologies. Without adoption of broader yield-enhancement strategies, manufacturers face greater risk as each new generation of process technology threatens to widen the gap between expected yield and actual yield.
Impact of Technology Trends
Market demand continues to drive IC design requirements toward greater functionality, higher clock speeds, and lower power requirements. To accommodate more demanding device performance objectives, silicon foundries are responding with sophisticated manufacturing technologies that combine sub-wavelength geometries with such advances as copper interconnect and low-k dielectrics. Designers' ability to exploit these manufacturing technologies results in larger, more complex ICs that can exhibit increased nanometer-related effects-and lower yield.
At nanometer geometries, leakage currents become significant, increasing overall power dissipation. Lower supply voltages used with fine-line geometries mean lower noise margins and more sources of signal-integrity (SI) problems. Higher frequency signals in nanometer wires increase the SI impact of problems such as crosstalk and coupling on circuit timing and function. Furthermore, at 500 MHz and above, clock and signal paths can take on distinctively analog behavior, requiring digital designers to adopt methods once largely the exclusive domain of analog engineers.
As clock rates continue to rise, designers need to further tighten design parameters to meet chip performance requirements, resulting in longer design cycles. At the same time, tight packing of fine-line features complicates accurate modeling, so simulated results diverge more radically from actual silicon performance. As features shrink, engineers also face greater difficulty in accounting for statistical device parameter variations, because device parametric variation and process standard deviations generally increase. To account for this increased variation, designers need to adopt more effective "design-centering" techniques and apply robust design techniques such as via redundancy and metal fill that do not otherwise directly contribute to design function.
Perhaps the most profound impact of emerging nanometer effects on yield lies in the implications for the development process. With today's tight margins, semiconductor companies need to apply specific yield-enhancing methods tuned to each particular IC design. As a result, designers now find themselves placed squarely in a position to directly influence manufacturing results. Companies can no longer expect manufacturing to solve yield problems well after tape-out. Post-processing of GDSII or mask data occur too late in development and can, at best, address only a small percentage of yield-reducing problems.
Consequently, successful nanometer design depends on the ability of designers to anticipate manufacturing concerns before tape-out. Using more accurate design-stage simulations and timing analysis techniques, designers must address the impact of manufacturing- and lithography-based distortions of wires, dielectrics, and devices to achieve acceptable yield or even working silicon. Indeed, the solution lies in deployment of a range of improved design-stage capabilities, including better device characterization, more accurate extraction, improved analyses for power, SI and electromigration analysis, as well as reticle design and wafer layout solutions. In this environment, electrical analysis and verification technologies become key enablers for design-specific yield enhancement.
Broader Yield Influencers
Conventional development methods are less effective for improving yield in modern processes because traditional process-related yield issues no longer strictly dominate yield (see Figure 3). At nanometer process nodes, performance and lithography issues begin to exert a more pronounced influence. As a result, the pursuit of enhanced yield now involves a broader agenda beyond conventional design-for-manufacturing (DFM) efforts such as design rule checking (DRC), optical proximity correction (OPC), and fracturing.
At nanometer technology nodes, performance and lithography effects begin to dominate as key influencers of yield, requiring more comprehensive yield-enhancement strategies. (Figure source: International Business Solutions, Global System IC (ASSP/ASIC) Service Management Report, May 200)
Nanometer yield enhancement demands adjustments across the full breadth of the design chain: Designers need to take manufacturing effects into account in early development, and manufacturing needs to consider design in applying more sophisticated yield-enhancing solutions following tape-out. For example, current manufacturing approaches apply corrections to every die structure, whether it is a critical net or a non-design related feature such as metal fill. Techniques such as OPC incur days-long run times, and the effort grows as the square of the number of objects. By focusing corrective actions just on design-critical elements, such post-processing methods can be applied more effectively despite increasingly massive amounts of data associated with large nanometer designs.
In this environment, yield success critically depends on a mutual collaboration by all participants in the design chain. Designers need to know that their design chain has been fully validated for target technology nodes through silicon characterization, silicon-validated intellectual property (IP), process design kits, and reference flows. By using manufacturing-aware tools, IP, and models, engineers can create nanometer designs that require substantially less correction later in manufacturing, lower mask complexity, faster turn-around time, and lower costs.
For their part, engineers using these design chains need to play a more significant role to effectively address manufacturing yield concerns at first silicon, into production ramp-up, and through profit-optimization during volume manufacturing. Companies can no longer afford to let design engineers throw designs "over the wall" to manufacturing and trust that manufacturing will optimize yield. Instead, to achieve effective yield-enhancement strategies, designers must consider manufacturing yield and DFM issues throughout the design cycle, using integrated tool suites that help them design complex devices with yield in mind. Indeed, engineers need to account for these concerns in each of the three phases of yield enhancement to improve first silicon, boost the ramp to volume, and improve profitability in volume production (see Figure 4).
With advanced manufacturing technologies, semiconductor companies need to account for yield-influencing factors at each stage: first silicon, ramp-to-volume, and volume production.
Yield Enhancement Phase I: Improving First Silicon
As part of their efforts, engineers begin to enhance yield through the use of yield-optimized library cells and optimized hard silicon IP cores. Manufacturers often pre-qualify cell libraries for a target process and include such features as antenna diodes in flip-flops to enforce antenna design rules. Beyond use of improved design techniques, however, yield improvement in nanometer designs depends increasingly on improved design centering, more accurate parasitic extraction, reliable analysis of power and SI effects, and use of design recommendations from silicon foundries.
At nanometer geometries, natural manufacturing variations can impact device performance, particularly for analog, mixed-signal, and radio-frequency (RF) designs, which are particularly sensitive to process variations, including lot-to-lot variations, chip-to-chip variations, and variations across an individual die. Design-centering techniques help engineers minimize yield loss due to these variations. Here, newer tools help designers synthesize the correct device geometries to meet specifications at the center of process-parameter spreads. For example, if analysis shows that a design would exhibit a low yield, engineers can apply automatic design-centering methods that add statistical corners to the design's goals and optimize feature sizes until the design is centered within the likely ranges of manufacturing effects (see Figure 5).
Without accurate analysis, a design could lie only partially in the region of feasibility (A). Advanced tools help engineers center a design by iteratively adding corners (B) until the design is recentered in the optimum feasibility region (C).
Improving First Silicon through Greater Accuracy
With previous process generations, designers have been able to protect designs from manufacturing-related variations by widening margins in timing and in physical layout. At advanced technology nodes, however, the impact of nanometer effects can exceed reasonable margins, resulting in non-functional first silicon and costly diagnostic efforts to unravel the sources of failure. Although the use of margins has helped ensure working first silicon, designers inevitably sacrificed other performance criteria or die area by increasing margin broadly, lacking the precise data needed to determine specifically what margins were actually needed. Furthermore, this approach can actually lengthen the design cycle and inevitably lead to the use of larger buffers, more power dissipation and heat, greater risk of SI and electromigration problems, as well as increased chip area. Accurate parasitic extraction provides the detailed data needed to reduce margins (se Figure 6), even in the face of manufacturing variations in advanced process technologies. Today's more accurate extraction tools are able to account for systematic process distortions, minimizing the need for excess margins and problems related to over-design.
Gross estimates of parasitics can cause designers to adjust margins beyond the ideal feasibility region for a design (A), but the use of more accurate parasitic data allows designers to reduce margins, maximizing performance and yield (B).
In fact, accurate parasitic extraction becomes critical when advanced manufacturing methods introduce performance variations in individual wires. For example, the use of copper interconnects leads to individual variations because chemical mechanical polishing (CMP) can wear down the top of copper wires, which are softer than the surrounding insulating dielectric. CMP can result in wires with uneven copper thickness across a chip, so even wires of equal length can exhibit variable parasitic delay. In turn, this variation in thickness causes variable interconnect sheet resistance and capacitance across the chip, leading to variable parasitic delay even for wires of equal length. For nanometer technologies, this delay variation can result in serious discrepancies between timing simulations and silicon performance. To reduce these CMP effects, manufacturers insert "dummy" metal to increase copper uniformity across a chip. For the designer, the challenge is to ensure that dummy metal insertion has minimal impact on signal wire resistance due to metal density and wire capacitance due to coupling.
With today's chip-design complexity, accurate and detailed parasitic RLCK extraction is critical for simulation and analysis to ensure high chip performance and yield. Advanced extraction tools provide accurate 2D and 3D modeling and characterization of advanced dielectrics, trapezoidal conductors, copper technology, and other technologies found in modern processes. With these more accurate extraction tools, designers can account for the manufacturing-related changes in resistance and capacitance, reducing margins to enhance design performance and yield.
Improving First Silicon through Enhanced SI and Power Analysis
With the availability of more accurate data and improved analysis methods, designers can address the growing impact of IR drop and SI on yield in nanometer design. Advanced SI tools can accurately determine the effects of noise on timing and function in complex designs. With these tools, designers can isolate victim nets with low noise immunity to avoid potential noise-related silicon failures well before tape-out
Power analysis has earned greater attention in nanometer design flows, because IR drop across large devices can introduce both set-up and hold timing violations that impact performance yield (see Figure 7). If IR drop impacts the clock network, the clock is delayed, which can result in hold time violations. Conversely, if IR drop impacts a signal net, the signal is delayed, which results in set-up time violations.
IR drop can occur on both signal and clock nets, causing both set-up and hold time violations in critical nets. Sophisticated IR drop analysis tools can use instance-based data to uncover these subtle timing problems prior to tape-out.
In the past, engineers have attempted to identify IR drop problems by applying a single de-rating factor to supply voltage across the entire chip. Running static timing analysis with simple de-rated power cannot show additional setup or hold time violations caused by IR-drop-related slew variations, because the uniform de-rating applies equally to all nets of the design. Designers can only identify these additional violations by including instance-based operating voltages in the static timing analysis flow, where each instance is analyzed against its own unique operating conditions. More advanced SI tools are now able to use this instance detail to calculate path delays more accurately by including the effects of both IR drop and SI problems in the same calculation.
Emerging power-grid signoff methods use a combination of static and dynamic approaches for comprehensive power integrity verification. Here, engineers use static methods to verify operation of the power network and then use dynamic methods to optimize nets for transient performance.
Designers use static IR drop analysis to identify global power routing issues, such as open circuits, lack of routing widths, lack of power straps, missing vias, and missing via arrays. Static analysis is also the preferred approach for power electromigration verification, because this approach reliably reveals the results of a design operating over an extended period of time.
Dynamic analysis reports IR drop transients on the power networks, typically caused by localized simultaneous switching of devices. Advanced tools can report the density and efficiency of de-coupling capacitors in a nanometer design. With these results, designers can identify where de-coupling capacitance can be optimized to reduce IR drop transients or lessen leakage.
Improving First Silicon through Foundry Recommendations
Along with the yield gains afforded by improved analysis techniques, designers can take advantage of foundry recommendations for physical designs. For example, foundries such as TSMC provide reference flows that call for redundant vias on normal signal lines and on wide metal lines if room is available. TSMC's reference flow defines a redundant via insertion approach comprising four different types of vias. For designers, advanced place-and-route tools can greatly simplify implementation of this type of sophisticated methodology by directly supporting the different types of vias recommended by the foundry.
In addition, design teams can improve yield by exploiting enhanced design rule sets being developed by foundries. Indeed, a design can technically achieve early silicon success yet not fully exploit the capabilities of advanced manufacturing capabilities. To help designers achieve the full potential of their manufacturing technologies, leading silicon foundries are beginning to augment required design rules with additional optional rule sets. Designers can leverage the augmented rule sets to identify specific areas of a design that are particularly sensitive to manufacturing effects because of their specific structure or geometry. This type of deep analysis will use more detailed models and incur longer run times, so the ability to identify specific regions and focus analysis on just those areas is vital to ensure rapid turn-around of optimized designs.
Yield Enhancement Phase II: Improving Ramp-to-Volume
The emergence of sophisticated optical lithography techniques has extended designers' responsibilities in facilitating a faster ramp-to-volume. Unlike previous process generations, where manufacturing engineers could independently apply mask corrections and optimizations, sub-wavelength lithography used in nanometer processes can distort wafer-imaged structures, physically changing design layout and altering circuit performance. Designers need to anticipate these distortions prior to tape-out to minimize risk and reduce sensitivity to manufacturing defects.
For nanometer process technologies, particularly at 65nm and below, the photomask shapes that represent individual on-chip geometries do not transfer accurately onto the wafer due to wavelength diffraction effects. Because the wavelength of the photoresist-exposing light source is longer than the dimensions of some of the structures being placed on the chip, the transferred images are distorted on the wafers themselves. Other process steps such as etching and oxide growth, among others, exacerbate the distortion. Without corrective action, inaccurate device-image replication will lead to large yield losses.
Silicon foundries apply reticle enhancement technology (RET) methods to deal with diffraction-induced distortions. RET typically comprises two types of corrections: PSM (phase-shift masking) and OPC. PSM and OPC can create smaller geometries for a given wavelength of light and can also reduce on-chip and chip-to-chip parameter variations. With PSM, the light source is split into two phases to avoid interference patterns and increase image resolution on the wafer.
OPC compensates for line shortening, corner rounding, and other distortions caused by features smaller than the wavelength of the exposing light. Here, the OPC technique augments the mask image with additional features that are smaller than the nominal mask design rules. OPC is typically required for more than two-thirds of the layers of 130nm design and virtually all of the layers at 90nm. Because the added OPC features are smaller than the nominal mask design rules, these features are much more difficult to generate and process. As a result, the indiscriminate use of OPC adds significant complexity to the physical database, dramatically increasing tool run-time and delaying time-to-volume.
With the addition of new lithography-aware tools in design chains, designers will be able to more efficiently account for sub-wavelength lithographic effects. As engineers design individual cells, these tools can quickly identify where potential problems may later arise in PSM or OPC. Furthermore, by passing along information about critical design structures to lithography, engineers can help focus OPC to specific regions of a design and help reduce OPC run times. As these tools move further upstream in the design chain, semiconductor companies will be able to minimize OPC requirements to produce masks of the lowest possible complexity, thus reducing costs while maximizing device performance and die yield.
Yield Enhancement Phase III: Improving Profitability
In classic development models, yield improvement relies on detailed process analysis and manufacturing diagnosis. Here, engineers carefully monitor the process to determine if it is within nominal specifications, and the foundry fine-tunes the process itself to the design to achieve maximum yield.
Advanced process-monitoring software provides engineers with a diagnostic environment that lets them more effectively analyze design intent and collate manufacturing information to develop better yield-enhancement solutions. Engineers may also use special failure-analysis equipment to isolate root causes of chip failures to identify any yield-affecting problems in the chip fabrication process.
Each yield enhancement in this stage directly contributes to greater profitability, so the ability to achieve maximum yield early in volume production will continue to provide a significant advantage. As a result, semiconductor companies will likely adopt emerging capabilities that tighten the flow of data between the factory floor and the design station. By improving their ability to anticipate yield improvements earlier in design, semiconductor companies will be able to achieve maximum profitability for even the most complex nanometer designs.
Conclusions
As the industry moves to complex nanometer processes, the classic approach that throws a design "over the wall" to manufacturing will inevitably result in failed silicon and little understanding of the corrections needed to restore function, much less maximize yield. Although semiconductor companies enjoyed a relatively steep ramp to volume production and quick time-to-profit for earlier processes, the manufacturing effects associated with nanometer processes threaten to flatten yield ramps and delay revenue. Even the use of more sophisticated post-processing RET strategies by themselves will be unable to achieve a significant improvement in yield if applied in isolation and without complementary actions taken earlier in design.
Nanometer yield enhancement requires a more collaborative approach involving all participants in the design chain, including designers, IP vendors, tool providers, and foundries. Instead of tuning a manufacturing process to each design, semiconductor companies and foundries will need to collaborate more actively to tune each design to the process. In turn, success in nanometer design depends on the ability to deploy a design chain that is itself attuned throughout to the manufacturing requirements of each specific design. Indeed, every aspect of product development impacts yield. By deploying manufacturing-aware tools and methods early in development, semiconductor companies can anticipate potential problems well before silicon. By addressing yield early and often throughout design, semiconductor companies can achieve a faster ramp to volume production and profit for complex nanometer designs.
About the Author
Dr. Levitt is currently vice president of Cadence's Design for Manufacturing business unit. He came to Cadence in 2002 as product-line vice president of design for manufacturing. He then moved into the role of vice president of research and development for nanometer analysis and verification and design for manufacturing at Cadence. Before joining Cadence, Dr. Levitt served as director of VLSI at Transmeta, director of silicon development at Sonics, and senior hardware manager at Sun Microsystems. He's also held numerous technical positions at Hewlett-Packard and Digital Equipment.
Dr. Levitt's work has been published in more than 30 publications. In 1996, he received the Sun Microsystem's Engineering Excellence Award. Dr. Levitt earned his master of science in electrical engineering and his doctorate in electrical engineering from the University of Illinois. He also earned a bachelor of science in computer engineering from Lehigh University.
