Presented By
IEC

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DesignCon East DesignCon

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Official Sponsor
infineon

Diamond Sponsor
Agilent

Associate Sponsors
Bayern Innovative edacentrum Fraunhofer IEE Si2 VSIA

Pre-registration is no longer available. To speed up the on-site registration process, please print out the following registration page and bring it with you to the registration counter located in the foyer outside the Ballsaal.

4 Step Registration
Step 1 Step 2 Step 3 Step 4


Step 1: Education Selection
Please complete the form below to register for this event.
- View Schedule
- Student / Professor Grant options
- Register via phone, fax, or mail

4-Day Conference Package (Best Value!) – €595
Includes access to the following:
  • Keynote addresses
  • Plenary and conference panels
  • Technical sessions (Tuesday and Wednesday)
  • TecForums (Monday and Thursday)
  • Receptions
  • Access to the exhibition floor
  • DesignCon proceedings
3-Day Program – €495
Includes access to the following:
  • Keynote addresses
  • Plenary and conference panels
  • Technical sessions (Tuesday and Wednesday)
  • TecForums (Monday or Thursday)
  • Receptions
  • Access to the exhibition floor
  • DesignCon proceedings
2-Day Program – €395
Includes access to the following:
  • Keynote addresses
  • Plenary and conference panels
  • Technical sessions (Tuesday and Wednesday)
  • Receptions
  • Access to the exhibition floor
  • DesignCon proceedings
1-Day Program Plus TecForums – €395
Includes access to the following:
  • Keynote address
  • Plenary and conference panels
  • 1 days of technical sessions (Tuesday or Wednesday)
  • 1 day of TecForums (Monday or Thursday)
  • Receptions
  • Access to the exhibition floor
  • DesignCon proceedings
1-Day Program – €250
Includes access to the following:
  • Keynote address
  • Plenary and conference panels
  • 1 day of technical sessions (Tuesday or Wednesday)
  • Receptions
  • Access to the exhibition floor
  • DesignCon proceedings
Monday TecForums – €250
Includes access to the following:
  • Monday TecForums
  • Keynotes
  • Plenary and conference panels
  • Receptions
  • Access to exhibition floor (Tuesday and Wednesday)
  • DesignCon proceedings
Thursday TecForums – €125
Includes access to the following:
  • Thursday TeForums
  • Complimentary Programming (Monday - Wednesday)
  • Access to exhibition floor (Tuesday and Wednesday)
  • DesignCon proceedings
Exhibits Only – €0 (€75 after 21 October)
Includes access to the following:
  • Keynote addresses
  • Plenary and conference panels
  • Receptions
  • Access to the exhibition floor
  Total Registration Fee $



To help us better prepare for your visit to Euro DesignCon, we ask that you take a moment to indicate which sessions you will be attending.
Monday, 24 October
9:00 – 12:00
TF-MA1: Process/Design Learning from Electrical Test
TF-MA2: Low Power Design Techniques for SOC and Microprocessors: An Industry Perspective
TF-MA3: Advances in Time and Frequency Domain Measurements, Modeling, and Signal Integrity
13:30 – 16:30
TF-MP1: Using SystemVerilog Assertions in an AMBA 3.0 (AXI) System Design Environment
TF-MP2: C/C++ Design Flow: From a C/C++ Reference to Silicon
TF-MP3: Recent Developments in Signal Integrity Measurements and Analysis Practical...
Tuesday, 25 October
9:40 – 10:20
1-TA1: Challenges in Power PC440-FS Soft Core Development: Timing Perspective
3-TA1: Evaluation of Temporal-Spatial Voltage Scaling for Processor-like Reconfigurable Architecture
5-TA1: S-Parameter Based Eye Diagrams of High Speed Links in Comparison to Direct Measurements...
6-TA1: At-Speed Scan Transition and Path Delay Testing Using On-chip PLL for High Frequency Devices
10:25 – 11:05
1-TA2: Galvanic Isolation using Capacitive Coupling: CMOS-technology Allows 100Mbps and High...
3-TA2: Raising the Level of Abstraction for Design and Verification: SystemC and SystemVerilog in...
5-TA2: Simulation for Electromagnetic Compatibility (EMC) and Signal Integrity (SI) in an Integrated...
6-TA2: ZBIST: The Memory BIST Architecture
11:10 – 11:50
1-TA3: Alternator Control ICA High Integration System IC with High Power Capability and Serial Interface
3-TA3: Build and Verify Sophisticated System-on-Chip (SoC) Designs in Minutes
5-TA3: Backplane Channels and Correlation between Their Frequency and Time Domain Performance
6-TA3: Transfer Functions for Serial Data Communications: Theory and Applications
14:00 – 14:40
1-TP1: Design and Thermal Management of Power Distribution Units for Automotive Applications
4-TP1: Creating a Provably Correct Design Methodology
5-TP1: Modeling of Gigabit Backplanes from Measurements
6-TP1: The Next Generation of Automated Test Pattern Generation
14:50 – 15:30
2-TP2: Static Timing Analysis in Ultra Deep Micron Technologies
4-TP2: Managing Verification of SoCs: An Integrated Framework for System, Design, Firmware
5-TP2-1: The Operational Impacts of Good 10GBPS Channel Design: A Look at Serdes Power...
5-TP2-2: Designing Transceiver FPGA's Using Advanced Calibration Techniques
Wednesday, 26 October
8:30 – 9:10
2-WA1: Physical Optimization Algorithms for Timing Closure
3-WA1: Full Chip Simulation Enables Pre-silicon Software Development
4-WA1: Coverage-driven Verification with SystemC Testbenches
5-WA1: Beyond 10Gbps: Next generation Serial Interfaces
A-WA1: Measurements of Impedance, Current and Worst-case Noise on Chip Power Delivery System
9:15 – 9:55
2-WA2: A Flexible and Adaptive Pipelining Concept for Low Latency Interconnects
3-WA2: DSP Synthesis: A Breakthrough for System-Level FPGA Designers
4-WA2: Technical and Managerial Data About Property Checking With Complete Functional Coverage
5-WA2: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems
A-WA2: The Recessed Probe Launch: A New Signal Launch for High Frequency Characterization...
10:00 – 10:40
2-WA3: Addressing Design for Manufacturability (DFM) Issues in Nanometer Designs and Beyond
3-WA3: A Novel Technique for VCO Design Having Multiple Tuning Ranges with Inbuilt Digital Controller
5-WA3-1: Infotainment Communication via PCS (Polymer Cladded Silica) Fibre for Car Application
5-WA3-2: The Duobinary Format: A New Application for an Idea Published Long-ago
A-WA3: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects and PCB Routability
14:00 – 14:40
2-WP1: Modeling Complex Silicon Effects in Nanometer Designs
3-WP1: Improving the IP Evaluation Process
4-WP1: Decomposing an ARM Architecture Specification into Assertions for Dynamic and Formal...
5-WP1: Impacts of Interconnect Solutions on Crosstalk within the via Construction at 10Gbps
14:50 – 15:30
2-WP2: EDA Platform: DFM Buzzword or True Technological Benefit
4-WP2: Using Coverage Driven Verification Techniques and Advanced Verification IP
5-WP2-1: Connector Footprint Optimization Enables 10 Gb+ Signal Transmission
5-WP2-2: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan
Thursday, 27 October (TecForums)
9:00 – 12:00
TF-THA1: Practical Guidance in Achieving Design Portability
TF-THA2: Discussing the Limitations and Accuracies of Time and Frequency Domain Analysis...

How did you learn about this program?
E-mail notice
Printed brochure
Telephone call/message
Web search
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Magazine advertisement:
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Cancellation and Refund Policy
Advance registration can be cancelled and refund made only if WRITTEN notice is postmarked prior to midnight, 24 September 2005. Facsimile (fax) transmitted cancellations must carry a transmittal time prior to midnight 24 September 2005, to receive a full refund. Participants who register after 24 September 2005 are responsible for full registration payment. No full or partial cancellations or refunds after 24 September 2005.

Other ways you can register:

Phone: +1-312-559-4600

Fax: +1-312-559-4111

Mail:
Euro DesignCon 2005
300 West Adams Street
Suite 1210
Chicago, IL 60606-5114 USA