Euro DesignCon 2005




	2004 Archive Highlights \| Schedule \| Exhibitor List \| Press Releases \| Sponsors Schedule Schedule view: By Date \| By Track Monday 11 October 9:00 -12:00 TF1: SystemC, Transaction-Level Modeling and Interfacing Standards TF2: Channel Compliance Test Utilizing Novel Statistical Eye Methodology 12:00 - 13:00 Monday Keynote Luncheon Address Hugo De Man, Co-Founder and Senior Research Fellow, IMEC 13:00 - 16:00 TF3: Advances in Platform ASICs TF4: M-LVDS in Practice: New Life for Multipoint Buses TF5: Introducing the Optical Internetworking Forum Common Electrical I/O Project 16:00-17:15 Technical Panel Design-for-Manufacturing to Minimize the Number of Re-Spins Panel Chair: Christelle Faucon, TSMC Tuesday 12 October 8:30 - 9:15 1-TA1: Formal Verification of a Key Block of the Tricore-2 Microprocessor 2-TA1: Low-Power System Design Techniques Using "uWatt" FPGAs 5-TA1: Simple Approach to Modeling of Power Delivery Networks and Components 6-TA1: HSDPA/WCDMA System Design... 9:30 - 10:15 1-TA2: Fast and Efficient Development of Hardware-Dependent Software for SoC Designs 2-TA2: Low-Power Design Optimization Methodology and Flow for Sub-90nm ASIC 5-TA2: How to Make Optimal Use of Signal Conditioning in 40-Gbps Copper Interconnects 6-TA2: C-Based Hardware Design for Wireless Applications 10:30 - 11:45 Plenary Panel: System-Level Design: Where is EDA? 12:00 - 12:30 Tuesday Keynote Address Dr. Andreas von Zitzewitz, Member of the Management Board and Chief Operating Officer, Infineon Technologies 12:30 - 14:30 Exhibition and Lunch 14:00 - 14:45 A-TP1: Implementing High-Speed RLDRAM II Memory Interfaces with FPGAs 1-TP1: The Four Pillars of Assertion-Based Verification 3-TP1: Substrate Noise Analysis and Minimization Techniques 5-TP1: The Evolution of Backplane Interconnect... 6-TP1: A Single DSP Core Communication Engine Solution... 15:00 - 15:45 A-TP2: Testing of High-Speed Serial I/O Interfaces Based on Spectral Jitter Decomposition 1-TP2: An Architecture Specification and Model-Based Verification Methodology 3-TP2: Modeling Simultaneous Switching Noise on High Density FPGAs 5-TP2: The Application of Equalisation to High-Speed Backplane Interfaces 6-TP2: Unique 1.6 GSPS CMOS 8-bit 1.8V ADC Delivers 7.5 ENOB Past Nyquist 16:00 - 17:15 Technical Panels Who benefits from Assertions? Panel Chair: Harry Foster, Chief Methodologist, Jasper Design Automation Have FPGA's Hit the Wall? Is ASIC Dead? What Silicon Solutions Should You Pick? Panel Chair: Gerhard Stelzer, Deputy Editor-in-Chief, Elektronik/Germany 16:30 - 18:30 Exhibition and Reception 17:00 - 20:00 European SystemC Users Group Meeting Wednesday, 13 October 8:30 - 9:15 2-WA1: High-Performance Network Protocol Processor - Architecture and C-Compiler 3-WA1: Physical Design Methodology for a 0.13um System on a Chip 4-WA1: Enabling the PCI Express Ramp - ATE-Based Testing of PCI Express 5-WA1: Transition to Surface-Mount... 9:15 - 10:00 2-WA2: A New Design Approach for Processor-Like Reconfigurable Hardware 3-WA2: Power Grid Topology for Nanometer Designs 4-WA2: Test Challenges And Possible Solutions For Multiple Gbps ICs 5-WA2: The Impact of Environmental Conditions on Channel Performance 10:15 - 11:00 A-WA3: Multi-Core Embedded Debug for Structured ASIC Systems 2-WA3: PCI-Express - IP for a Next Generation I/O Interconnect 4-WA3: Identifying Sources of Jitter 5-WA3: Manufacturing Process and Electrical Behavior of Back-Drilled Holes... 7-WA3: Can MATLAB/Simulink Co-Exist with VHDL-AMS? 11:00 - 11:45 A-WA4: Formal Verification of Block-Level Assertions 2-WA4: TriCore 2 - A Microarchitectural Exploration of a Multithreaded Embedded Processor 4-WA4: Solving DSM Test Challenges 5-WA4: A New Signal Integrity Test and Measurement Architecture for Serial 10 Gb/s Interfaces 7-WA4: Development Tool Support Architecture for High-Performance... 12:00 - 12:30 Wednesday Keynote Address Edward W. (Ned) Barnholt, Chairman, President and Chief Executive Officer, Agilent Technologies 12:30 - 14:30 Exhibition and Lunch 14:00 - 14:45 3-WP1: From DRC Clean to Yield Optimization... 4-WP1: DFT Challenges for Effective Deployment... 5-WP1: Enabling Terabit Backplanes Using Channel Optimization... 7-WP1: Application and Evaluation of High-Level Automated Analysis... 15:00 - 15:45 2-WP2: Design Optimization Methodologies... 3-WP2: Electrical/Physical Co-design in Case of a Robust 3.3-V, 10.7-MHz... 4-WP2: Total Test Quality for Nanometer Designs 7-WP2: Wireless Networks Reshape Automotive Diagnostic Systems 16:00 - 17:15 Technical Panels Design-for-Test Considerations for Mergeable Cores Panel Chair: Peter Harrod, CPU Design and Test Manager, ARM Ltd Design Productivity: What Is It, And Why To Measure? Panel Chair: Martin Radetzki, Head Consulting, edacentrum 16:30 - 18:30 Exhibition and Reception Thursday 14 October 9:00 - 12:00 TF6: Applying Physics-Based Analysis to the Design and Verification... TF7: Signal Integrity Analysis for Clock and DataCom Applications © 2005 International Engineering Consortium Terms of Use \| Privacy Statement \| Contact Us