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2004 Archive
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Schedule
14:00-14:45
Tuesday 12 October
3-TP1: Substrate Noise Analysis and Minimization Techniques
Manoj Sundareswaran, Design Engineer, Infineon Technologies
Rama Kotapally, Senior Design Engineer, Infineon Technologies
Balamurugan Selvaraj, Senior Design Engineer, Infineon Technologies
Ganesan Nagasubramanian, Staff Engineer, Infineon Technologies

This paper presents a study and analysis on substrate noise effects in mixed signal integrated circuits and the techniques to minimize them. When many static gates switch simultaneously they inject a lot of noise on to common substrate through parasitic resistance, capacitance and inductance. Noise generation can be controlled by shielded routing, reducing the package inductance, double bonding, lowering the voltage swing. Some amount of noise reduction can also be achieved by careful floor planning to isolate the analog and digital circuits. This paper concentrates on arriving at an effective methodology to minimize the effects of the package inductance, interconnect capacitance, substrate resistance and capacitance on substrate noise.