DesignCon East 2005




	Schedule Schedule View: By Date \| By Track Keynotes Monday, September 19 12:30 – 1:00 pm Monday Keynote Luncheon Address Raul Camposano, Senior Vice President and Chief Technology Officer, Synopsys Tuesday, September 20 Noon – 12:30 pm Tuesday Keynote Address Michael Paczan, Chief Technology Officer, Power.org Initiative, Systems and Technology Group, IBM Corporation Wednesday, September 21 Noon – 12:30 pm Wednesday Keynote Address Donald Desbiens, Vice President and Chief Technology Officer, Fairchild Semiconductor Plenary Panel Wednesday, September 21 10:30 am – 11:45 am Plenary Panel: Standardization and Commoditization of Hardware Design Technical Panels Monday, September 19 4:45pm – 6:00pm Technical Panel: Bypass Capacitors: How to Determine their Inductance Tuesday, September 20 3:45pm – 5:00pm Technical Panel: The Role of Verification at the Architecture Definition Stage Technical Panel: Advances in Signal Integrity Testing Wednesday, September 21 3:45pm – 5:00pm Technical Panel: Integrating Crosstalk, Timing and Signal Integrity Analysis: How and Why Technical Panel: Jitter Characterization Challenges TecForums Monday, September 19 9:00am – 12:00pm TF-MA1: Incisive Advanced Verification Flow TF-MA2: Recent Developments in Signal Integrity Measurements and Analysis TF-MA3: Discussing the Limitations and Accuracies of Time and Frequency Domain Analysis of Physical Layer Devices 1:30pm – 4:30pm TF-MP1: Structured ASIC Design – Approaches and Trends TF-MP2: Inductance of Bypass Capacitors: How to Define, How to Measure, How to Simulate TF-MP3: Multi-Gigabit Serial Channel Design Methodology – From Architecture, Through Prototype, To Physical Measurement Verification TF-MP4: Advanced Memory System Design Feature and Implementation of High-Performance DDR2 Memory Systems TecPreview Tuesday, September 20 11:00 am – 11:20 am TP-TA4: Addressing DSM Design Risks with Maskless Structured ASICs Track 1 \| IC Design and Test Tuesday, September 20 8:30am – 9:10am 1-TA1: ATM-Related Protocols Functional Verification for Communication Processor 9:20am – 10:00am 1-TA2: Using Yield-Focused Design Methodologies to Speed Time-To-Market 10:10am – 10:50am 1-TA3: Essential Measurement Considerations When Using Extracted-Clock Timing References 11:00am – 11:40am 1-TA4: Methodology for Jitter Measurement Correlation and Consistency 2:15pm – 2:55pm 1-TP1: Standards-compliant IP Design – Advantages, Problems, and Future Directions 3:00pm – 3:40pm 1-TP2: Extraction and Implementation of Effective Mismatch Models Wednesday, September 21 8:50am – 9:30am 1-WA1: DesignCon Paper Award, Presented at DesignCon 2005: Fearless Partitioning: An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SOC Track 2\| FPGA and Structured ASIC Design Wednesday, September 21 8:50am – 9:30am 2-WA1: VHDL-200X: The Future of VHDL 9:40am – 10:20am 2-WA2: Solving Signal Integrity Challenges with Advanced Package Designs 2:15pm – 2:55pm 2-WP1: Design for Portability 3:00pm – 3:40pm 2-WP2: Customized Synthesis for 90nm Structured ASICs: Delivering Higher Performance, Faster Time to Market, and Reduced Work on the Back End Track 3\| Functional Verification Tuesday, September 20 8:30am – 9:10am 3-TA1: Top-Down Post-Layout Mixed-Signal Design Verification Methodology for FPGA-Embedded Multi-Gigabit Transceiver 9:20am – 10:00am 3-TA2: Integrating On-Chip Debug Instrumentation and EDA Verification Tools 10:10am – 10:50am 3-TA3: Front End Power Sequencing Simulation of Voltage Islands 11:00am – 11:40am 3-TA4: Creating a Provably Correct Design Methodology 2:15pm – 2:55pm 3-TP1: eVC for Functional Simulation of Voltage/Temperature Variation and Noise on an I/O Bus 3:00pm – 3:40pm 3-TP2: Bringing Formal Property Verification into the Mainstream Wednesday, September 21 9:40am – 10:20am 3-WA2: Seamless Unified Chip/Multi-Core/Core Simulation Environment Track 4\| Power and Packaging Tuesday, September 20 2:15pm – 2:55pm 4-TP1: DesignCon Paper Award, Presented at DesignCon 2005: Measurements of Impedance, Current and Worst-Case Noise on Chip Power Delivery System under Operating Conditions 3:00pm – 3:40pm 4-TP2: Bypass Filter Design Considerations for Modern Digital Systems: A Comparative Evaluation of the Big "V", Multipole, and Many Pole Bypass Strategies Wednesday, September 21 8:50am – 9:30am 4-WA1: Design of a Low-Power Differential Repeater Using Low-Voltage Swing and Charge Recycling 9:40am – 10:20am 4-WA2: Joint Study of Simultaneous Switching Noise and IO Return Current For a CMOS FPGA Package 2:15pm – 2:55pm 4-WP1: A VITA-Based Framework for Ruggedized COTS Electronics with Emphasis on Liquid Cooling - VITA 48 3:00pm – 3:40pm 4-WP2: A Black-Box Frequency Dependent Model of Capacitors for Frequency Domain Simulations Track 5\| High-Speed Interconnect Tuesday, September 20 9:20am – 10:00am 5-TA2: DesignCon Paper Award, Presented at DesignCon 2005: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan Method 10:10am – 10:50am 5-TA3: PCB Transmission-Line Modeling for Multi-Gbps Link Analysis 11:00am – 11:40am 5-TA4: Modeling of Infiniband Cable Assemblies from Measurements 2:15pm – 2:55pm 5-TP1: Simplified Design and Modeling of Surface Mount Connector Pad Transitions for Applications at 10 Gbps 3:00pm – 3:40pm 5-TP2: Feasibility of 40- to 50-Gbps NRZ Interconnect Design for Terabit Backplanes Wednesday, September 21 8:50am – 9:30am 5-WA1: Novel time domain scaling technique for crosstalk characterization 9:40am – 10:20am 5-WA2: Creating Repeatable 10 Gb/s Channels in an Uncertain World 2:15pm – 2:55pm 5-WP1: Meeting the PWB Needs for High Speed Data Transmission 3:00pm – 3:40pm 5-WP2: Employing LVDS Chips to Optimize FPGA Interface Performance Track 6\| Board and System-Level Design Tuesday, September 20 8:30am – 9:10am 6-TA1: Resolving Jitter in Modulated Clock Systems 9:20am – 10:00am 6-TA2: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems 10:10am – 10:50am 6-TA3: The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Rates 11:00am – 11:40am 6-TA4: DesignCon Paper Award, Presented at DesignCon 2005: Performance Model for Inter-Chip Busses Considering Bandwidth and Cost 2:15pm – 2:55pm 6-TP1: Air and Liquid Cooling Solutions for Orthogonal Card Packaging Architectures 3:00pm – 3:40pm 6-TP2: New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links Wednesday, September 21 8:50am – 9:30am 6-WA1: Connector footprint optimization enables 10 Gb+ signal transmission 9:40am – 10:20am 6-WA2: Connectorless Logic Analyzer Probing: Mechanical and Electrical Advantages 2:15pm – 2:55pm 6-WP1: Design of Embedded Capacitors in PCBs and Organic Chip Packages using Ultra-Thin Substrates 3:00pm – 3:40pm 6-WP2: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects, and PCB Routability © 2005 International Engineering Consortium Terms of Use \| Privacy Statement \| Contact Us