DesignCon East has been a sister conference to our very successful Santa-Clara based DesignCon program in the Boston area for the last three years. While the initiative has been successful in some ways, in other ways the event has not matched overall industry objectives. Consequently, IEC will not conduct DesignCon East in 2006.

DesignCon 2006 was a very successful event this year and has already been reserved for DesignCon 2007, January 29 - February 1, 2007, at the Santa Clara Convention Center. DesignCon 2007 exhibit space is currently available for reservation and we are expecting another record-breaking year with over 150 exhibiting companies.

DesignCon Paper Award Winners Winners are selected from a group of finalists chosen by the Technical Program Committee. Awards are determined based on the quality of the written technical paper, as well as its presentation at the conference. View the award-winning papers>>

The day began with three TecForums composed of speakers from Agilent Technologies, Cadence Design Systems, and Wavecrest. The in-depth three-hour sessions covered issues concerning verification flow, signal-integrity measurement and analysis, and a comparison of time and frequency domain techniques for analyzing physical-layer devices. Raul Camposano, Senior Vice President and Chief Technology Officer, Synopsys, delivered the keynote address at the TecForum luncheon, "The New Ubiquitous Design Concern: Manufacturability." Dr. Camposano observed how deliberate steps taken at the design, lithography, and process stages can improve IC manufacturability, which has become an area of increasing concern as geometries shrink to 45 nanometers and below. The luncheon keynote address was followed by four more TecForums, highlighting: Structured ASIC design Power distribution networks, Multi-gigabit serial channel design Advanced memory system design Monday wrapped up with a Technical Panel led by Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems. The panel addressed how to determine the inductance of bypass capacitors, a continuation of the series of DesignCon panels on power distribution networks.

The second day of DesignCon East 2005 began with technical papers from six different tracks, covering chip-level design and verification, power and packaging issues, signal integrity, and PCB design. The Tuesday keynote address was delivered by Michael Paczan, Chief Technology Officer, Power.org Initiative, Systems and Technology Group, IBM Corporation. He discussed the innovative approach to intellectual property management that the Power.org Initiative represents, extending the principles of the open-source movement to hardware design. The afternoon Technical Panels were led by Sunil Kakkar, Chief Technologist, Verification, Freescale Semiconductor India, Ltd. and Michael Lauterbach, Director, Product Management, LeCroy. The panels addressed the role of verification at the architecture definition stage and advances in signal-integrity testing. Sponsored by eASIC, the TecPreview delivered today discussed a new structured ASIC product line dedicated to reducing cost and development time. Today was also the opening day for the Technology Exhibition. With the exhibition floor 60 percent larger than last year, there were more opportunities to see the latest design tools and products from leading organizations. Attendees had the opportunity to go on the new DesignTOUR, with four lucky attendees winning prizes.

The last day of the conference ended with a full day of educational content. Highlights of the day included a plenary panel chaired by Wayne Morrison, Vice President, TCS Sales and Applications Engineering, Teradyne. The panel discussion centered on the effect of standardization on hardware design. While it may seem that standards drive products toward commoditization, designers can still create innovative implementations of standards to differentiate products. Wednesday's keynote address was delivered by Don Desbiens, Vice President and Chief Technology Officer, Fairchild Semiconductor. Mr. Desbiens reviewed how changing demands for power delivery and management have affected the design and packaging of power controllers, amplifiers, and drivers, and the impact on designs utilizing these chips. The two afternoon Technical Panels were led by Robert Haller, Principal Consultant, Signal Integrity Software, and Christopher Loberg, Design and Manufacturing Market Segment Manager, Tektronix. Mr. Haller's panel discussed integrating crosstalk, timing, and signal-integrity analysis, while Mr. Loberg's panel addressed jitter characterization challenges. The second day of the Technology Exhibition continued with leading organizations delivering the latest design tools and products. Attendees also took the DesignTOUR, with four more attendees winning great prizes.