FOR IMMEDIATE RELEASE

U.S. Contact: Kim Simpao
Phone: +1-773-315-7779
E-Mail: ksimpao@iec.org

IEC Congratulates DesignCon 2010 Paper Award Winners

The International Engineering Consortium (IEC) gives recognition to the Paper Award Winners from DesignCon 2010's conference and exhibition

CHICAGO – March 10, 2010 – The International Engineering Consortium today announced the winners of the 2010 DesignCon Paper Awards in recognition for their outstanding contributions to the educational goals of DesignCon 2010.

"We extend our congratulations to the Design Paper Award winners for their hard work and dedication in serving the semiconductor industry," commented IEC president, John Janowiak. "We are fortunate to have witnessed this caliber of expertise throughout the DesignCon educational program."

Winners were chosen from the DesignCon 2010 technical program Paper Award finalists papers. The Technical Program Committee selected the Award papers based on written merit and quality of presentation.

The 2010 DesignCon Paper Award winners include the following individuals in their respective categories:

Chip-Level Design

Andres Takach - Creating C++ IP for High Performance Hardware Implementations of FFTs

Luke Teyssier - Strong Encryption and Correct Design Are Not Enough: Protecting Your Secure System from Side Channel Attacks

Board and System Design

Allen F. Horn III, John W. Reynolds, Patricia A. LaFrance, and James C. Rautio - Effect of Conductor Profile on the Insertion Loss, Phase Constant, and Dispersion in Thin High Frequency Transmission Lines

Kevin Hinckley, Douglas Winterberg, Mike Ballou, Gustavo Blando, Jason R. Miller, Roger Dame, Alexander Nosovitski, Gregory Truhlar, Shelley Begley and Istvan Novak - Introduction and Comparison of an Alternate Methodology for Measuring Loss Tangent of PCB Laminates

Interconnect Design

Eric Bogatin, Don DeGroot, Colin Warwick and Sanjeev Gupta - Frequency Dependent Material Properties: So What?

Jason R. Miller, Gustavo J. Blando and Istvan Novak - Additional Trace Losses due to Glass-Weave Periodic Loading

High-Speed Design and Test Category

Ransom Stephens and John Calvin - A New Method for Receiver Tolerance Testing Using Crest Factor Emulation

Istvan Novak, Yasuhiro Mori, and Mike Resso - Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range

Power and RF Design Category

Shishuang Sun, Larry D Smith and Peter Boyle - On-Chip PDN Noise Characterization and Modeling

Xiaoxiong Gu, Renato Rimolo-Donadio, Zhenwei Yu, Francesco de Paulis, Young H. Kwark, Matteo Cocchini, Mark B. Ritter, Bruce Archambeault, Albert Ruehli, Jun Fan and Christian Schuster - Fast Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis

Award winning papers and finalists papers will be featured throughout the year in the DesignCon newsletter and InfoVault, and on-line resourse for the DesignCon community. For more information, visit www.designcon.com, or contact Kim Simpao at ksimpao@iec.org or +1-773-315-7779.

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About the IEC
A nonprofit organization, the IEC is dedicated to catalyzing technology and business progress worldwide in a range of high—technology industries and their university communities. Since 1944, the IEC has provided high—quality educational opportunities for industry professionals, academics, and students.

In conjunction with industry—leading companies, the IEC has developed an extensive, free, on—line educational program. The IEC conducts industry-university programs that have substantial impact on curricula. It also conducts research and develops publications, conferences, and technological exhibits that address major opportunities and challenges of the information age.

More than 70 leading high—technology universities are IEC affiliates, and the IEC handles the affairs of the Electrical and Computer Engineering Department Heads Association and Eta Kappa Nu, the honor society for electrical and computer engineers. Please visit www.iec.org